tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
tangxifan
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c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
tangxifan
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99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
tangxifan
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2f1aceda67
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[Doc] Update documentation about architecture naming rules
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2021-01-12 18:01:24 -07:00 |
tangxifan
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9fa49c401c
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[Arch] Add openfpga architecture which uses 4 global clocks
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2021-01-12 18:00:22 -07:00 |
tangxifan
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16b4e89326
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[Doc] Update documentation for VPR architectures
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2021-01-12 17:57:40 -07:00 |
tangxifan
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7ccdff4543
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[Arch] Add an architecture using 4 clocks
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2021-01-12 17:55:57 -07:00 |
tangxifan
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3790f2c26a
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[Benchmark] Add 2-clock micro benchmark
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2021-01-12 17:48:52 -07:00 |
tangxifan
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a0b9f2b40d
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Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
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2021-01-11 10:02:31 -07:00 |
tangxifan
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30aaab0c2e
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[Test] Deploy new test to CI
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2021-01-10 11:53:49 -07:00 |
tangxifan
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65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |
tangxifan
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e58e1e86c2
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
tangxifan
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18d2a8ce19
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[Flow] Add new script for fixed device layout using global tile clock
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2021-01-10 11:08:02 -07:00 |
tangxifan
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aaf582acc5
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[Arch] Bug fix
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2021-01-10 11:05:57 -07:00 |
tangxifan
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1c68e43acf
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[Test] Add new test case for registerable I/O architecture
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2021-01-10 11:00:21 -07:00 |
tangxifan
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f21d22f691
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[Doc] Update README for new architectures
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2021-01-10 10:54:59 -07:00 |
tangxifan
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dfb3e32147
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[Arch] Add openfpga archiecture for registerable I/O
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2021-01-10 10:54:41 -07:00 |
tangxifan
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853e7b1a40
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[Arch] Add vpr architecture where I/O can be either combinational or registered
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2021-01-10 10:54:09 -07:00 |
tangxifan
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43418cd76b
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[Test] Deploy pipeplined and2 to test cases
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2021-01-10 10:28:22 -07:00 |
tangxifan
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6521aa2e7a
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[Benchmark] Bug fix in pipelined and2 benchmark
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2021-01-10 10:27:59 -07:00 |
tangxifan
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4412bbd084
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[Benchmark] Add a micro benchmark to test pipelined architecture
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2021-01-10 10:21:30 -07:00 |
tangxifan
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0c808bec41
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[Doc] Add clarification for defining multi-bit global tile ports
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2021-01-09 20:00:16 -07:00 |
tangxifan
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4124777948
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[Tool] Set (x,y) to be optional XML syntax in tile annotation
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2021-01-09 18:56:41 -07:00 |
tangxifan
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2324edc522
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[Doc] Update documentation for upgraded tile annotation
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2021-01-09 18:55:16 -07:00 |
tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
tangxifan
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0b74575606
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[Arch] Update arch using global reset tile port
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2021-01-09 18:04:55 -07:00 |
tangxifan
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7b24da267a
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[Arch] Remove port size XML syntax
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2021-01-09 16:30:46 -07:00 |
tangxifan
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9f12b25a24
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[Arch] Add port size to global port defined thru tile annotation
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2021-01-09 16:23:28 -07:00 |
tangxifan
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0f5f0a3527
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[Arch] Add x,y coordinates to global port definition
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2021-01-09 15:50:09 -07:00 |
tangxifan
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a14a56772a
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[Arch] Introduce new XML syntax for global port in tile annotation
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2021-01-09 15:48:42 -07:00 |
tangxifan
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e86a929154
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Merge pull request #168 from lnis-uofu/yosys_bump_submodule
Bumping yosys submodule with the latest changes done in yosys repo re…
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2021-01-09 13:32:30 -07:00 |
Lalit Sharma
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8a5741b1ae
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Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
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2021-01-08 07:08:24 -08:00 |
tangxifan
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0bb1f92ed8
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Merge pull request #167 from lnis-uofu/dev
Support on Using Scan-chain Flip-flop in Configuration Chain
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2021-01-07 10:00:34 -07:00 |
tangxifan
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cde26597ed
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[Tool] Bug fix in scan chain builder calling
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2021-01-04 18:45:47 -07:00 |
tangxifan
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226f6b8d6d
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
tangxifan
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62eb6e24cb
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[Test] Add SCFF configuration chain test case to CI
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2021-01-04 17:42:49 -07:00 |
tangxifan
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804b721a19
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[Tool] Bug fix in the configuration chain connection builder
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2021-01-04 17:41:29 -07:00 |
tangxifan
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a813c9016b
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[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
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2021-01-04 17:39:13 -07:00 |
tangxifan
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06af30ef10
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[Test] Add test case for the SCFF usage in configuration chain
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2021-01-04 17:30:19 -07:00 |
tangxifan
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bfd305b5a5
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[Tool] Patch the bug in finding data output ports for CCFF
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2021-01-04 17:22:30 -07:00 |
tangxifan
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709ee1b842
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[HDL] Update dff netlist for SCFF used in configuration chain
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2021-01-04 17:17:35 -07:00 |
tangxifan
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c97a92d628
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[Arch] Patch openfpga architecture for ccff circuit model port requirement
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2021-01-04 17:15:50 -07:00 |
tangxifan
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cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
tangxifan
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cb34be0dc0
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[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
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2021-01-04 15:13:54 -07:00 |
tangxifan
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294ad97d38
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[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
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2021-01-04 14:56:49 -07:00 |
tangxifan
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722a9bcf63
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[HDL] Add scan-chain DFF cell with configuration enable signal
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2021-01-04 14:31:26 -07:00 |
tangxifan
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a9f91513f6
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Merge pull request #156 from lnis-uofu/quicklogic_test
Adding a testcase to run yosys quicklogic flow
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2020-12-24 23:08:40 -07:00 |
Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
tangxifan
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67b9a5a9c0
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Merge pull request #163 from lnis-uofu/tangxifan-patch-1
Dead link patch to fontpage README
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2020-12-21 14:01:45 -07:00 |
tangxifan
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25b0b84133
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Broken link patch to fontpage README
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2020-12-21 11:33:36 -07:00 |