Lalit Sharma
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2a1c484055
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Merge remote-tracking branch 'origin/master' into quicklogic_test
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2020-12-20 23:43:02 -08:00 |
tangxifan
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668c531e8e
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Merge pull request #162 from lnis-uofu/bump_yosys
Bumping latest updates to yosys submodule
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2020-12-18 11:31:48 -07:00 |
Lalit Sharma
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6d75108bc4
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Bumping latest updates to yosys submodule
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2020-12-18 04:02:12 -08:00 |
Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
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2020-12-18 03:18:46 -08:00 |
Lalit Sharma
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1f994319fd
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Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
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2020-12-16 04:19:56 -08:00 |
Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
Lalit Sharma
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3e4732e8b2
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Merge remote-tracking branch 'origin/master' into quicklogic_test
Merging latest updates from master.
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2020-12-16 03:50:51 -08:00 |
tangxifan
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6b15ae6805
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Merge pull request #152 from lnis-uofu/replace_yosys
Replace yosys
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2020-12-15 08:24:39 -07:00 |
Lalit Sharma
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0e7c04878c
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Merge remote-tracking branch 'origin/master' into replace_yosys
Merging latest changes from master.
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2020-12-14 20:57:26 -08:00 |
Lalit Sharma
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682f9fa802
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Merge remote-tracking branch 'origin/master' into replace_yosys
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2020-12-14 20:18:54 -08:00 |
tangxifan
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7f297114b6
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Merge pull request #160 from lnis-uofu/dev
[Git] Add labeler for pull requests
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2020-12-14 15:13:34 -07:00 |
tangxifan
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5a0fbe7705
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[Git] Use main version of labeler
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2020-12-14 13:40:40 -07:00 |
tangxifan
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1e19039b9a
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[Git] Use specific path to labeler configuration file
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2020-12-14 13:37:28 -07:00 |
tangxifan
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279d259fd7
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[Git] Use compatible ubuntu version for labeler
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2020-12-14 12:16:45 -07:00 |
tangxifan
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abc1b51771
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[Git] Add labeler for pull requests
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2020-12-14 11:38:17 -07:00 |
tangxifan
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e51c90db46
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Merge pull request #159 from lnis-uofu/dev
Add default pull request template to the right position that Github requires
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2020-12-14 11:26:05 -07:00 |
tangxifan
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4204e98ffa
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[Git] Add default pull request template to the right position that Github prefers
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2020-12-14 10:29:53 -07:00 |
tangxifan
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5bda464ca0
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Merge pull request #158 from lnis-uofu/dev
Bug fix on the incompatible sphinx bibtex version
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2020-12-14 10:26:54 -07:00 |
Lalit Sharma
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2b6dbb7cd6
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Adding target compile in Makefile that just compiles without updating submodules
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2020-12-14 09:25:50 -08:00 |
tangxifan
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024bc17b84
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[Doc] Bug fix on the incompatible sphinx bibtex version. Constrain to the right version.
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2020-12-14 09:37:45 -07:00 |
Lalit Sharma
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3ccd6b80dd
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Updating compile.rst file with updated compilation steps
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2020-12-13 21:04:10 -08:00 |
Lalit Sharma
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3a82bae1ac
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Updating compilation steps
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2020-12-11 03:51:23 -08:00 |
Lalit Sharma
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b621c4f694
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Removing yosys-symbiflow-plugins compilation from CMakefile
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2020-12-10 21:44:57 -08:00 |
Lalit Sharma
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6991848f97
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Removing yosys-symbiflow-plugins submodule and will be added separately later via another PR
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2020-12-10 21:06:08 -08:00 |
tangxifan
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780be05079
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Merge pull request #154 from lnis-uofu/dev
Add pull request template
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2020-12-10 16:39:59 -07:00 |
Lalit Sharma
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0ee3efb306
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Adding a testcase to run yosys quicklogic flow
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2020-12-10 02:41:43 -08:00 |
Lalit Sharma
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f805a62f96
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Updating yosys branch to quicklogic-rebased
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2020-12-09 23:36:13 -08:00 |
Lalit Sharma
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3b302dd538
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Updating yosys URL to pick from QuickLogic-Corp repo, this is done till this repo is merged to mainstream repo
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2020-12-09 22:25:51 -08:00 |
Lalit Sharma
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760b8bd7ad
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Adding tcl8.6-dev package as CI dependency
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2020-12-08 21:14:48 -08:00 |
Lalit Sharma
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07dfd35e12
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Adding yosys-symbiflow-plugins as submodule and adding tcllib as dependency in CI
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2020-12-08 20:35:57 -08:00 |
tangxifan
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c278bb0a5f
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[Git] Format fix on pull request template
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2020-12-08 17:29:30 -07:00 |
tangxifan
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e20c8d578e
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[Git] Format pull request template and add more OpenFPGA-related topics
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2020-12-08 17:27:48 -07:00 |
tangxifan
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6383946ae6
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[Git] Add pull request template
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2020-12-08 17:16:50 -07:00 |
tangxifan
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6b50bbf986
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Merge pull request #134 from lnis-uofu/ganesh_dev
Support Delay Customization in OpenFPGA Task Configuration File
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2020-12-08 15:32:48 -07:00 |
Lalit Sharma
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8a2681f99f
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Re-setting option YOSYS_ENABLE_TCL to ON, as yosys compilation depends on tcl
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2020-12-08 09:21:25 -08:00 |
Lalit Sharma
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3a7bc77871
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Correcting the syntax for CI run
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2020-12-08 09:14:05 -08:00 |
Lalit Sharma
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d7ec481e9e
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Adding updates to checkout submodules
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2020-12-08 08:52:35 -08:00 |
Lalit Sharma
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ed9535693c
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Updating CMakeList.txt to compile yosys
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2020-12-08 01:29:36 -08:00 |
Lalit Sharma
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460bf9d3bd
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Adding yosys sub-module instead of yosys folder
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2020-12-07 23:54:18 -08:00 |
Lalit Sharma
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9cee60ddbf
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deleting yosys local folder to replace it with corresponding yosys sub-module
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2020-12-07 23:52:20 -08:00 |
Laboratory for Nano Integrated Systems (LNIS)
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c5d9bac126
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Merge pull request #150 from lnis-uofu/dev
Misc Updates
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2020-12-06 15:44:37 -07:00 |
tangxifan
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d11a3d9fef
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[Tool] Avoid outputting signal initialization codes because they are bulky
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2020-12-06 14:29:16 -07:00 |
tangxifan
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cb2bd2e31c
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[Tool] Remove register ports for mini local encoders (1-bit data out)
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2020-12-06 14:21:54 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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2eaff52c13
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Merge pull request #149 from lnis-uofu/dev
Netlist/Module size Reduction for Routing Multiplexers
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2020-12-05 13:44:20 -07:00 |
tangxifan
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6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
tangxifan
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6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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e1563c93d8
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Merge pull request #148 from lnis-uofu/dev
Organize Routing Multiplexer Verilog Netlist
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2020-12-05 09:34:49 -07:00 |
tangxifan
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0da92ad888
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[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
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2020-12-04 22:16:51 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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09fa83ddfc
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Merge pull request #147 from lnis-uofu/dev
Support I/O tiles in the center part of FPGA grid layout
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2020-12-04 19:30:31 -07:00 |
tangxifan
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b717903ca1
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[CI] Deploy new test to CI
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2020-12-04 18:51:30 -07:00 |