tangxifan
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aa9521b23b
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
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2020-09-14 15:57:44 -06:00 |
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tangxifan
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eecfd186f0
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[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
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2020-09-14 15:46:10 -06:00 |
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tangxifan
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9bf0e772a3
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[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
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2020-09-14 15:45:35 -06:00 |
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tangxifan
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4b3142c4ee
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[Architecture File] Patch openfpga architecture with default circuit model definition
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2020-08-23 15:13:28 -06:00 |
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tangxifan
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9101ba1021
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[Architecture Language] Update openfpga architecture files for default models
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2020-08-23 14:55:44 -06:00 |
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tangxifan
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6c925dcded
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[regression test] Add more tests for thru channels and deploy to CI
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2020-08-19 20:11:37 -06:00 |
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tangxifan
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881672d46a
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update thru channel arch for avoid buggy pin locations
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2020-08-19 19:52:35 -06:00 |
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tangxifan
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bf08e1841c
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add new test case using thru channels
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2020-08-19 17:58:34 -06:00 |
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tangxifan
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f0bc6f83f1
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disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
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2020-08-19 15:34:59 -06:00 |
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tangxifan
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18735894f9
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bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
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2020-08-19 15:27:30 -06:00 |
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tangxifan
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3273f441fe
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bug fix in the flagship vpr arch
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2020-08-19 15:23:20 -06:00 |
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tangxifan
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aa4a9b28cc
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start testing the initial offset in the flagship architecture
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2020-08-19 15:03:46 -06:00 |
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tangxifan
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f64079641d
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bug fix in flagship vpr arch with frac mem and dsp
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2020-08-19 12:43:58 -06:00 |
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tangxifan
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d7efdf35b6
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add custom pin location to the flagship vpr arch with frac mem and dsp
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2020-08-19 11:15:25 -06:00 |
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tangxifan
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dbd93e429d
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now pro_blif.pl can accept customized clock name
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2020-08-19 09:43:44 -06:00 |
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tangxifan
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743167521a
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add Verilog design for fracturable 32k memory
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2020-08-18 21:13:46 -06:00 |
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tangxifan
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42b5ea2cb1
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bug fix in openfpga arch for frac mem and dsp
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2020-08-18 20:42:36 -06:00 |
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tangxifan
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3ee4e10aa8
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bug fix in the frac mem & DSP vpr arch
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2020-08-18 17:25:45 -06:00 |
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tangxifan
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098859fe06
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bug fix in the frac memory & DSP architecture
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2020-08-18 15:05:51 -06:00 |
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tangxifan
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21c7eaa9cf
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add 36-bit fracturable multiplier Verilog
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2020-08-18 14:06:08 -06:00 |
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tangxifan
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f833e0ec66
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add a flagship architecture using fracturable memory and dsp
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2020-08-17 17:49:51 -06:00 |
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tangxifan
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1ca2829868
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update readme for vpr architecture naming
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2020-08-17 13:54:26 -06:00 |
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tangxifan
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cadf29022e
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add README to explain the organization of regression tests
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2020-07-28 13:44:06 -06:00 |
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tangxifan
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f33422d4d7
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add regression test to track runtime on big fpga devices using practical benchmarks
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2020-07-28 12:38:42 -06:00 |
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tangxifan
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534c609e17
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add fixed layouts to a flagship architecture to test bitstream generation runtime
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2020-07-28 11:51:50 -06:00 |
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tangxifan
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a156807559
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enrich basic regression tests to cover more critical microbenchmarks
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2020-07-27 19:47:43 -06:00 |
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tangxifan
|
5d83abb2cf
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bug fix in read architecture bitstream and regression tests
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2020-07-27 19:37:05 -06:00 |
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tangxifan
|
31e7a753a6
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-07-27 19:22:16 -06:00 |
ganeshgore
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747c062f86
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BugFix : Flow script accepts extra OpenFPGA arguments
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2020-07-27 18:10:43 -06:00 |
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tangxifan
|
50cc4dfba3
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classify regression test to dedicated categories
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2020-07-27 17:18:59 -06:00 |
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tangxifan
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5595ee9052
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refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
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tangxifan
|
cec6bf0b6f
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add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
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tangxifan
|
4174fbf77d
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add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |
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tangxifan
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a3eba8acbe
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update task files using the new syntax on SHELL variables
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2020-07-27 15:25:49 -06:00 |
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tangxifan
|
615b557dc4
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-07-27 14:48:23 -06:00 |
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tangxifan
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dc7012d590
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update regression tests for split fabric_bitstream commands
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2020-07-27 14:24:48 -06:00 |
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ganeshgore
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45af056304
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TASK_NAME and TASK_DIR variables are avaialble in config file now
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2020-07-27 14:14:57 -06:00 |
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ganeshgore
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0e46e0d857
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Updated task.conf format to have transparent shell variables
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2020-07-27 14:08:58 -06:00 |
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tangxifan
|
177de90822
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bug fix in example scripts
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2020-07-26 22:10:04 -06:00 |
|
tangxifan
|
f687774452
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bug fix in template scripts
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2020-07-26 21:46:03 -06:00 |
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tangxifan
|
41a76126b9
|
add fabric bitstream writer to CI
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2020-07-26 21:44:42 -06:00 |
|
tangxifan
|
c87f6b75b9
|
add test case for FPGA-SPICE
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2020-07-24 19:12:35 -06:00 |
|
tangxifan
|
020154b0cd
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add depopulate crossbar test case
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2020-07-24 18:06:02 -06:00 |
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tangxifan
|
021fedbc12
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update fabric key to synchronize with new module/instance naming
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2020-07-24 12:55:40 -06:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
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2020-07-22 21:55:59 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
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2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
ca867ea6fa
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add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
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tangxifan
|
87ef7f9f99
|
add power gate example architecture
|
2020-07-22 20:06:10 -06:00 |
|
tangxifan
|
8ade40713a
|
add missing architecture for CI
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2020-07-22 14:07:39 -06:00 |
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tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |