tangxifan
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415fd9a8fa
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[core] code format
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2024-09-21 21:39:30 -07:00 |
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tangxifan
|
9e461284d0
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[core] standardize API for clock network intermeidate drivers
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2024-09-21 21:38:32 -07:00 |
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tangxifan
|
1332d426c7
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[core] code format
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2024-09-20 17:42:53 -07:00 |
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tangxifan
|
965ee2190e
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[core] support intermediate driver in clock arch
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2024-09-20 17:42:26 -07:00 |
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tangxifan
|
8e04d473f2
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[core] code format
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2024-09-18 21:10:31 -07:00 |
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tangxifan
|
44a07704ff
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[core] add check codes for last stage pgl model
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2024-09-18 21:10:02 -07:00 |
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tangxifan
|
f6b645fd25
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[core] code format
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2024-09-18 17:44:55 -07:00 |
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tangxifan
|
82878063c1
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[core] syntax
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2024-09-18 17:32:04 -07:00 |
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tangxifan
|
47e30c3e4b
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[core] support last stage mux
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2024-09-18 17:26:44 -07:00 |
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tangxifan
|
82cf7bbb8c
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[core] Add verbose mode on find_node() for clock rr graph
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2024-08-02 17:47:41 -07:00 |
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tangxifan
|
ae1100ceba
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[core] cleanup debug message
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2024-08-02 17:05:59 -07:00 |
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tangxifan
|
ad38b52a23
|
[lib] code format
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2024-08-02 12:41:00 -07:00 |
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tangxifan
|
1a13c5f815
|
[lib] now fabric key assistant can cross-check mismatches between reference and input fabric keys
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2024-08-02 12:31:55 -07:00 |
chungshien-chai
|
766df0a1b5
|
Improve Port Parser
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2024-07-31 12:19:30 -07:00 |
|
chungshien-chai
|
0d9f1a3c6b
|
Forward searching the config bit + some minor refactor
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2024-07-28 19:12:34 -07:00 |
|
chungshien-chai
|
9882394c8b
|
Use archfpga_throw
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2024-07-28 02:53:18 -07:00 |
|
chungshien-chai
|
2a3d69aded
|
Update code based on feedback
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2024-07-28 02:37:15 -07:00 |
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chungshien-chai
|
933155b08f
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Update test flow
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2024-07-27 23:52:54 -07:00 |
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chungshien-chai
|
e60777d23e
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Use Bitstream Setting XML
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2024-07-26 01:36:49 -07:00 |
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tangxifan
|
c96f899c53
|
[core] code format
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2024-07-10 15:07:26 -07:00 |
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tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
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2024-07-10 15:01:18 -07:00 |
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tangxifan
|
b2fc47a12a
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[core] reworked i/o for clock network files
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2024-07-10 14:34:54 -07:00 |
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tangxifan
|
079e6f2fca
|
[core] add new syntax to support from_pin and to_pin for internal driver in clock network
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2024-07-10 14:28:28 -07:00 |
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tangxifan
|
0f78803759
|
[core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs
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2024-07-09 20:47:15 -07:00 |
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tangxifan
|
578d7c8ec0
|
[core] fixed a bug on region tap point identification
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2024-07-01 20:58:41 -07:00 |
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tangxifan
|
73b30841a7
|
[lib] typo
|
2024-07-01 20:56:27 -07:00 |
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tangxifan
|
60e6e27e54
|
[core] fixed a bug on tap point identificatin
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2024-07-01 20:45:55 -07:00 |
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tangxifan
|
a85a6f1674
|
[core] code format
|
2024-07-01 17:57:10 -07:00 |
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tangxifan
|
70428fd969
|
[lib] add sanity checks on global port name and clock network's global port name
|
2024-07-01 17:56:29 -07:00 |
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tangxifan
|
df23daf026
|
[lib] sanity check on global port name and from pin name of tap points
|
2024-07-01 17:37:16 -07:00 |
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tangxifan
|
7c487eadc9
|
[core] now clock network keep port info in a native data structure
|
2024-07-01 16:58:23 -07:00 |
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tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
1fd974d544
|
[core] fixed a bug where clock network size cannot impact global port on top module
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2024-06-29 17:35:47 -07:00 |
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tangxifan
|
34fb003911
|
[core] replace width syntax with global port name
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2024-06-29 10:46:00 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
|
2024-06-26 17:58:26 -07:00 |
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tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
|
2024-06-26 17:40:11 -07:00 |
|
tangxifan
|
3b25e42720
|
[lib] syntax
|
2024-06-26 15:51:00 -07:00 |
|
tangxifan
|
381a8cb535
|
[lib] clock tap syntax are reworked. Support region, single, all and from/to ports
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2024-06-26 15:41:56 -07:00 |
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tangxifan
|
4640e74e7e
|
[core] code format
|
2024-06-25 12:25:16 -07:00 |
|
tangxifan
|
66af73e91e
|
[lib] now accept reset and set in programmable clock network
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2024-06-25 12:24:46 -07:00 |
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tangxifan
|
7bcbd8a88b
|
[core] code format
|
2024-06-25 11:44:50 -07:00 |
|
tangxifan
|
3b2c13402a
|
[core] syntax
|
2024-06-25 11:44:25 -07:00 |
|
tangxifan
|
31d4b4c402
|
[core] now support add internal drivers to clock tree
|
2024-06-25 11:27:22 -07:00 |
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tangxifan
|
272d78eb43
|
[test] add a new unit test
|
2024-06-24 19:13:36 -07:00 |
|
tangxifan
|
22bee35fd1
|
[lib] mem allocate
|
2024-06-24 18:47:56 -07:00 |
|
tangxifan
|
36ef555dda
|
[lib] add example arch for clock arch with internal drivers
|
2024-06-24 18:33:47 -07:00 |
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tangxifan
|
2eda2825b7
|
[lib] syntax
|
2024-06-24 18:28:42 -07:00 |