Lin
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a785a57520
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small bug mod
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2024-08-18 22:41:40 -07:00 |
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Lin
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755959a890
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add cb cx write function
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2024-08-08 02:54:02 -07:00 |
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Lin
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e45619b22d
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write sb
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2024-08-08 01:00:35 -07:00 |
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Lin
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9c67950a75
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preload functions
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2024-08-07 03:20:45 -07:00 |
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Lin
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72a90a4d8f
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add preload function
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2024-08-05 19:42:21 -07:00 |
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Lin
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c726744154
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add sb unique modules
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2024-08-05 02:23:47 -07:00 |
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Lin
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5ac19ea628
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read unique blocks io
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2024-08-04 20:51:27 -07:00 |
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Lin
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7f426d5939
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add commands
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2024-08-02 03:10:10 -07:00 |
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Lin
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48a386c9b6
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add read and write uniqueblocks commands
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2024-08-02 01:43:01 -07:00 |
tangxifan
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ad8ad25250
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[core] format
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2024-05-31 19:44:40 -07:00 |
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tangxifan
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93ebbef851
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[core] fixed a bug
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2024-05-31 19:42:50 -07:00 |
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tangxifan
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514ec2f02e
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[core] code format
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2024-05-31 18:02:46 -07:00 |
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tangxifan
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2d10be9edb
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[core] code comments
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2024-05-31 18:00:24 -07:00 |
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tangxifan
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f9cd01636d
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[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
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2024-05-31 17:57:36 -07:00 |
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tangxifan
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212abecc27
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[core] syntax
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2024-05-31 17:41:49 -07:00 |
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tangxifan
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348d474bfd
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[core] more debuggin messages
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2024-05-31 17:40:19 -07:00 |
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tangxifan
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c565264e7d
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[core] more debuggin messages
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2024-05-31 17:14:42 -07:00 |
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tangxifan
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6dc31bf892
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[core] fixed a bug on missing net sync up during repack
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2024-05-31 16:53:59 -07:00 |
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tangxifan
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5b35f567d2
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[core] detailed messages to trace why some nets are no sync
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2024-05-31 16:00:10 -07:00 |
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tangxifan
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5adc1be204
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[core] syntax
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2024-05-31 15:50:27 -07:00 |
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tangxifan
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a9ccc277bd
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[core] more debugging message
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2024-05-31 15:49:34 -07:00 |
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tangxifan
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937e279c59
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[core] adding more debugging messages
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2024-05-31 15:43:51 -07:00 |
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tangxifan
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7a7fc679a8
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[core] enable more debugging message in repacker
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2024-05-31 14:52:59 -07:00 |
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tangxifan
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edb50f1b4d
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[core] update debug messages
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2024-05-31 14:37:46 -07:00 |
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tangxifan
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48c0b4b219
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[core] fixed a bug where net name is not shown correctly on wire LUTs
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2024-05-31 12:45:12 -07:00 |
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tangxifan
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74e94b855e
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[core] fixed a bug where gsb OPIN name does not match the switch block module
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2024-05-29 10:27:10 -07:00 |
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tangxifan
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52ae484a7c
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[core] fixed a bug on messed up wire connections for OPINs
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2024-05-20 13:50:31 -07:00 |
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tangxifan
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ca6e2f9831
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[core] code format
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2024-05-20 13:41:35 -07:00 |
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tangxifan
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4a791249bf
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[core] fixed a bug on requirement wire model for direction connection which is part of a cb
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2024-05-20 12:52:07 -07:00 |
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tangxifan
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b554a3d855
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[core] code format
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2024-05-19 17:24:38 -07:00 |
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tangxifan
|
56aaa6a1f4
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[core] sytax
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2024-05-19 17:23:48 -07:00 |
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tangxifan
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065d77c679
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[core] supporting opin connection to cb in tiles
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2024-05-19 17:04:24 -07:00 |
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tangxifan
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9079056871
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[core] now connect OPIN to CB in top-level module
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2024-05-19 14:27:36 -07:00 |
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tangxifan
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918bf79ca3
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[core] update vtr and developing caches for OPIN lists just for connection blocks
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2024-05-19 14:10:00 -07:00 |
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tangxifan
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772da3006b
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[core] code format
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2024-05-18 22:19:17 -07:00 |
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tangxifan
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304f34525e
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[core] syntax
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2024-05-18 22:17:52 -07:00 |
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tangxifan
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b533ea4060
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[core] now cb module include OPIN nodes
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2024-05-18 22:00:02 -07:00 |
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tangxifan
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926b9e9739
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[core] code format
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2024-05-18 12:33:19 -07:00 |
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tangxifan
|
3b93bea3d1
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[core] syntax
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2024-05-18 12:29:38 -07:00 |
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tangxifan
|
0d8c21ca84
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[core] add new type 'part_of_cb' for tile direct connections
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2024-05-17 18:59:53 -07:00 |
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tangxifan
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7848bdaeac
|
[core] code format
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2024-05-09 22:50:49 -07:00 |
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tangxifan
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5f37d63061
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[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
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2024-05-09 19:38:26 -07:00 |
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tangxifan
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7dc2c4951c
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[core] add missing header required by clang-11+
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2024-05-05 21:56:56 -07:00 |
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tangxifan
|
3d8107487c
|
[core] code format
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2024-05-03 10:21:39 -07:00 |
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tangxifan
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c7501cb9b7
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[core] fixed the bugs when there are module renaming
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2024-05-03 10:20:19 -07:00 |
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tangxifan
|
f41a5e8b89
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[core] fixed some bugs
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2024-05-02 22:49:06 -07:00 |
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tangxifan
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c557b0104a
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[core] avoid unwanted tab
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2024-05-02 21:34:12 -07:00 |
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tangxifan
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b85ec28eb8
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[core] code format
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2024-05-02 21:17:17 -07:00 |
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tangxifan
|
d3b1e562ad
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[core] fixed some bugs on format
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2024-05-02 21:11:20 -07:00 |
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tangxifan
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bf24382f19
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[core] code format
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2024-05-02 18:33:07 -07:00 |