tangxifan
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f311a034bb
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[FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path``
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2022-02-01 12:17:02 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
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tangxifan
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6a260cadbf
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[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
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2021-06-29 15:42:23 -06:00 |
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tangxifan
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7ac7de789e
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[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
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2021-06-29 15:26:40 -06:00 |
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tangxifan
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90163fab6c
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[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
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2021-06-25 15:06:07 -06:00 |
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tangxifan
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2bb514c51a
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[Tool] Support time unit in writing simulation information file
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2021-06-25 10:33:29 -06:00 |
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tangxifan
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d9d57aad42
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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tangxifan
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57a24570f5
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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tangxifan
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1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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b010fc1983
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add warning to force formal_verification_top_netlist enabled
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2020-02-27 13:28:21 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |