tangxifan
|
520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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tangxifan
|
04f0fbebf7
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plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
|
tangxifan
|
190449c06f
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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tangxifan
|
4b56b755f2
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refactored instanciation of routing modules in top module
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2019-10-14 21:06:10 -06:00 |
|
tangxifan
|
bd6a0c6a55
|
refactored grid instance addition to top module
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2019-10-14 17:47:10 -06:00 |
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tangxifan
|
f779ad7ecf
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bug fixing for global and gpio port wiring; start refactoring top-level module
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2019-10-14 15:53:04 -06:00 |
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tangxifan
|
997bfdbb95
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move the refactored function for physical block Verilog generation to a new source file
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2019-10-07 16:03:15 -06:00 |
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tangxifan
|
3ca6f08aa4
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start refactoring physical block Verilog generation
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2019-10-06 19:27:55 -06:00 |
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tangxifan
|
d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
|
d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
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tangxifan
|
f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
|
tangxifan
|
99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
|
fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
|
63f40f48fa
|
develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
|
tangxifan
|
27b619554d
|
add stats for verilog modules
|
2019-08-23 20:23:42 -06:00 |
|
tangxifan
|
ad06e9c98c
|
plug in module manager
|
2019-08-23 20:23:41 -06:00 |
|
tangxifan
|
fcb31e4c24
|
add stats for verilog modules
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2019-08-23 18:41:16 -06:00 |
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tangxifan
|
8eebca9daa
|
plug in module manager
|
2019-08-23 17:39:29 -06:00 |
|
tangxifan
|
aa7f3bef7f
|
fixed bugs in configure pb_rr_graph and dependence on testbenches
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2019-08-16 18:20:30 -06:00 |
|
tangxifan
|
d2d8af5416
|
bug fixing for pb_type num_conf_bits and num_iopads stats
|
2019-08-13 17:34:09 -06:00 |
Baudouin Chauviere
|
8f5ad2eb67
|
Snapshot of progress
|
2019-07-02 10:10:48 -06:00 |
|
Baudouin Chauviere
|
7c742f1cbb
|
Stable, is_explicit propagated through the code. Not implemented though except for muxes
|
2019-06-27 10:29:57 -06:00 |
|
Baudouin Chauviere
|
0ce9846e47
|
Stable, unfinished
|
2019-06-26 16:54:41 -06:00 |
|
Baudouin Chauviere
|
87ddca9f57
|
commiting current work. Stable but function not implemented yet
|
2019-06-26 14:22:02 -06:00 |
|
tangxifan
|
c879e7f6c5
|
fixed a critical bug when instanciating Connection blocks
|
2019-06-26 11:33:02 -06:00 |
|
tangxifan
|
d50fb7ee19
|
fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
|
tangxifan
|
8a8f4153ce
|
use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
|
2019-06-10 12:50:10 -06:00 |
|
tangxifan
|
e31407f693
|
start cleaning up SDC generator with new RRGSB data structure
|
2019-06-10 10:57:26 -06:00 |
|
tangxifan
|
02b48d036d
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
tangxifan
|
924136e7a2
|
Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
|
2019-05-24 15:10:08 -06:00 |
|
tangxifan
|
eef1312325
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |
|
tangxifan
|
be4643b8a6
|
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
|
2019-05-10 10:21:06 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |