Commit Graph

157 Commits

Author SHA1 Message Date
tangxifan 9c66a35bf6 [arch language] Now circuit library will automatically identify the default circuit model if needed 2020-08-23 14:06:03 -06:00
tangxifan b83319bf14 [Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group 2020-08-23 13:48:22 -06:00
tangxifan 161d660837 update documentation for the initial offset when mapping physical pins 2020-08-19 15:00:46 -06:00
tangxifan 3eea12ceae added a new XML syntax: initial offset for physical mode pin mapping 2020-08-19 14:43:44 -06:00
tangxifan 2712c354a9 now physical pb_port binding support multiple ports 2020-08-18 12:38:56 -06:00
tangxifan 35af0dd676 streamline fabric bitstream file format 2020-07-27 16:34:43 -06:00
tangxifan 92d2d2d849 add fabric bitstream XML writer 2020-07-26 21:00:57 -06:00
tangxifan a3d22c56e3 bug fix in FPGA-SPICE 2020-07-24 19:51:32 -06:00
tangxifan 6d046efc52 add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE 2020-07-24 16:25:27 -06:00
tangxifan f573fa3ee0 move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
2020-07-22 18:47:12 -06:00
tangxifan de4586217f now device binding is not mandatory for circuit models 2020-07-14 12:04:22 -06:00
tangxifan e2b492f184 add circuit model tech binding 2020-07-13 20:35:10 -06:00
tangxifan 62fd0947f5 using a unified string to replace multi net names to save memory of bitstream database 2020-07-08 16:28:20 -06:00
tangxifan 824b56f14c fabric key can now accept instance name only; decoders are no longer part of the key 2020-07-06 16:42:33 -06:00
tangxifan 1ad6e8292a move constants from verilog domain to common so that FPGA-SPICE can share 2020-07-05 11:39:46 -06:00
tangxifan 2a9377b3f4 use encoded address in storage of fabric bitstream to save memory 2020-07-03 15:12:29 -06:00
tangxifan 70d9678578 reserve child block in bistream manager 2020-07-03 14:04:10 -06:00
tangxifan 7d9c36aae1 use length instead of msb in bitstream manager for block bits to save memory 2020-07-03 12:06:15 -06:00
tangxifan 2783fda344 use index range instead of vector for block bitstream 2020-07-03 11:42:38 -06:00
tangxifan 6ea857ae6c use fast method to inquire number of bits and blocks in bitstream databases 2020-07-03 10:55:25 -06:00
tangxifan 6397cbe9d2 remove unused data in bitstream manager to compact memory usage 2020-07-03 10:35:35 -06:00
tangxifan 246b4d5ac6 reserve block bits to save memory 2020-07-02 21:52:32 -06:00
tangxifan 043fb54206 remove unused data in bitstream database 2020-07-02 20:53:18 -06:00
tangxifan 9799fea48f optimizing bitstream storage 2020-07-02 19:33:53 -06:00
tangxifan dee4be96af reserve all the input/output net storage in bitstream manager 2020-07-02 19:17:34 -06:00
tangxifan f97e3bfba6 add timer to openfpga shell 2020-07-02 18:02:33 -06:00
tangxifan e82d0d9f34 drop id list in bitstream manager to save memory usage 2020-07-02 16:18:32 -06:00
tangxifan 9f19c36a89 use char in fabric bitstream to save memory footprint 2020-07-02 15:56:50 -06:00
tangxifan 405824081b reserve configuration blocks and bits in bitstream manager builder to be memory efficient 2020-07-02 15:28:52 -06:00
tangxifan 9d32a5b81f add alias name support for fabric key 2020-06-27 14:59:53 -06:00
tangxifan b36da17a08 bug fix for directory creation when the input is an empty string 2020-06-25 10:34:34 -06:00
tangxifan e2d3ac78ec skip empty lines in OpenFPGA shell 2020-06-25 10:18:05 -06:00
tangxifan aded675633 rename files in fpga bitstream library to be consistent with conventions 2020-06-21 13:06:39 -06:00
tangxifan 2f33c35a4f add example XML file for bitstream 2020-06-20 19:05:44 -06:00
tangxifan 3bcdd0e1d4 clean up writer format for bitstream 2020-06-20 19:01:33 -06:00
tangxifan 1e763515b3 bug fix in bitstream parser and writer 2020-06-20 18:39:21 -06:00
tangxifan 675a59ecb8 Move fpga_bitstream to the libopenfpga library and add XML reader 2020-06-20 18:25:17 -06:00
tangxifan a5055e9d26 add support about loading external fabric key 2020-06-12 13:03:11 -06:00
tangxifan 3499b4d3e7 add fabric key writer for top-level module 2020-06-12 10:41:34 -06:00
tangxifan f081cef495 add fabric key library 2020-06-12 00:07:04 -06:00
tangxifan 58807bfcb3 remove simulation settings from openfpga arch data structure 2020-06-11 19:31:16 -06:00
tangxifan f26550141f add missing files 2020-06-11 19:31:16 -06:00
tangxifan 15f087598c split simulation settings to a separated XML file 2020-06-11 19:31:15 -06:00
tangxifan 8267dad8ef add decoder support for Z signals 2020-06-11 19:31:14 -06:00
tangxifan b8c449d520 add comments for decoding functions to help debugging the frame-based decoders 2020-06-11 19:31:11 -06:00
tangxifan 65df309419 bug fixing for frame-based configuration protocol and rename some naming function to be generic 2020-06-11 19:31:10 -06:00
tangxifan 3a0d3b4e95 fix the broken CI/regression tests due to incorrect file path 2020-06-11 19:31:10 -06:00
tangxifan 3a26bb5eef add advanced check in configurable memories 2020-06-11 19:31:09 -06:00
tangxifan 62c506182c start developing frame-based configuration protocol 2020-06-11 19:31:09 -06:00
tangxifan f52b5d5b4c use error code in read_arch command 2020-06-11 19:31:07 -06:00