ad8ad25250
[core] format
2024-05-31 19:44:40 -07:00
93ebbef851
[core] fixed a bug
2024-05-31 19:42:50 -07:00
514ec2f02e
[core] code format
2024-05-31 18:02:46 -07:00
2d10be9edb
[core] code comments
2024-05-31 18:00:24 -07:00
f9cd01636d
[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
2024-05-31 17:57:36 -07:00
212abecc27
[core] syntax
2024-05-31 17:41:49 -07:00
348d474bfd
[core] more debuggin messages
2024-05-31 17:40:19 -07:00
c565264e7d
[core] more debuggin messages
2024-05-31 17:14:42 -07:00
6dc31bf892
[core] fixed a bug on missing net sync up during repack
2024-05-31 16:53:59 -07:00
5b35f567d2
[core] detailed messages to trace why some nets are no sync
2024-05-31 16:00:10 -07:00
5adc1be204
[core] syntax
2024-05-31 15:50:27 -07:00
a9ccc277bd
[core] more debugging message
2024-05-31 15:49:34 -07:00
937e279c59
[core] adding more debugging messages
2024-05-31 15:43:51 -07:00
7a7fc679a8
[core] enable more debugging message in repacker
2024-05-31 14:52:59 -07:00
edb50f1b4d
[core] update debug messages
2024-05-31 14:37:46 -07:00
48c0b4b219
[core] fixed a bug where net name is not shown correctly on wire LUTs
2024-05-31 12:45:12 -07:00
74e94b855e
[core] fixed a bug where gsb OPIN name does not match the switch block module
2024-05-29 10:27:10 -07:00
52ae484a7c
[core] fixed a bug on messed up wire connections for OPINs
2024-05-20 13:50:31 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
4a791249bf
[core] fixed a bug on requirement wire model for direction connection which is part of a cb
2024-05-20 12:52:07 -07:00
b554a3d855
[core] code format
2024-05-19 17:24:38 -07:00
56aaa6a1f4
[core] sytax
2024-05-19 17:23:48 -07:00
065d77c679
[core] supporting opin connection to cb in tiles
2024-05-19 17:04:24 -07:00
9079056871
[core] now connect OPIN to CB in top-level module
2024-05-19 14:27:36 -07:00
918bf79ca3
[core] update vtr and developing caches for OPIN lists just for connection blocks
2024-05-19 14:10:00 -07:00
772da3006b
[core] code format
2024-05-18 22:19:17 -07:00
304f34525e
[core] syntax
2024-05-18 22:17:52 -07:00
b533ea4060
[core] now cb module include OPIN nodes
2024-05-18 22:00:02 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
7848bdaeac
[core] code format
2024-05-09 22:50:49 -07:00
5f37d63061
[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
2024-05-09 19:38:26 -07:00
7dc2c4951c
[core] add missing header required by clang-11+
2024-05-05 21:56:56 -07:00
3d8107487c
[core] code format
2024-05-03 10:21:39 -07:00
c7501cb9b7
[core] fixed the bugs when there are module renaming
2024-05-03 10:20:19 -07:00
f41a5e8b89
[core] fixed some bugs
2024-05-02 22:49:06 -07:00
c557b0104a
[core] avoid unwanted tab
2024-05-02 21:34:12 -07:00
b85ec28eb8
[core] code format
2024-05-02 21:17:17 -07:00
d3b1e562ad
[core] fixed some bugs on format
2024-05-02 21:11:20 -07:00
bf24382f19
[core] code format
2024-05-02 18:33:07 -07:00
a2fb84dfa9
[core] add fabric hierarchy writer
2024-05-02 18:30:20 -07:00
4d3447f773
[core] rework fabric hierarchy writer
2024-05-02 18:05:38 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
08bd6d00d3
[core] code format
2024-04-11 15:04:08 -07:00
79970719b4
[core] fixed a bug where regex breaks
2024-04-11 14:59:14 -07:00
f63ea06c4e
[core] now support regular expression in module name for fabric pin physical location output
2024-04-11 14:30:27 -07:00
5960cc14aa
[core] fixed a bug
2024-04-11 13:04:47 -07:00
6f94399767
[core] code format
2024-04-10 22:53:52 -07:00
971f0e8838
[core] add a new option '--show_invalid_side'
2024-04-10 22:52:36 -07:00
tangxifan
chungshien