9020577e80
Support SVG in Sphinx Latex building ( #220 )
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* [Doc] Try use image converter instead of svg2pdf which requires more dependencies
* [Doc] Add img converter to conf.py
* [Doc] Bug fix in importing imgconverter package
* [Doc] Try to fix the bug when importing python packages
* [Doc] bug fix
* [Doc] Try to use imgconverter rather than cairo
* [Doc] Add svg to latex config in sphinx configuration file
* [Doc] Try cairo svg converter
* [Doc] Correct bugs in compiling latexpdf
* [Doc] Use latest image in building readthedocs
* [Doc] Now use readthedocs docker image in building online documentation
* [Doc] Correct typo in readthedocs setting
* [Doc] Try to use inkscape converter as imgconverter converted SVG to black images
* [Doc] Try RSVG
2021-02-07 18:53:16 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
9b5c64f35f
[Doc] Update documentation about disable_packing syntax
2021-02-04 16:41:24 -07:00
d83158654c
[Doc] Add a draft documentation about the bitstream setting
2021-02-01 22:33:17 -07:00
0e16638dc2
[Doc] Update documentation about the changes on activity files
2021-01-29 11:49:07 -07:00
78ad9cd000
[Doc] Add version command/option to documentation
2021-01-27 16:06:45 -07:00
d53d3963d4
[Doc] Broken link fix in config protocol documentation
2021-01-26 14:05:11 -07:00
9fefe1502f
[Doc] Typo fix on write_fabric_key option
2021-01-25 15:18:16 -07:00
dd0680246a
[Doc] Typo fix on fabric key command
2021-01-25 14:12:40 -07:00
1ba7e0663f
Merge pull request #176 from lnis-uofu/dev
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Documentation Formatting
2021-01-24 21:11:49 -07:00
e18c533657
[Doc] Add new openfpga shell command to documentation
2021-01-24 14:48:56 -07:00
815468ac65
[Doc] Add shortcut to call pin constraint option to documentation
2021-01-20 09:20:51 -07:00
977ff52cb1
[Doc] Format openfpga command documentation by using option views
2021-01-19 20:26:38 -07:00
e9dc708d66
[Doc] Group file format documentation into a unified section
2021-01-19 19:44:44 -07:00
ac8c63553a
[Doc] Add file format index file
2021-01-19 18:07:53 -07:00
fbb5c0cf8f
[Doc] Add pin constraints to documentation
2021-01-19 18:04:45 -07:00
c7f02601ab
[Doc] Add repack design constraints to documentation
2021-01-17 12:59:46 -07:00
c4d3e7c50c
[Doc] Update documentation for the new XML syntax in simulation settings
2021-01-15 12:30:26 -07:00
0c808bec41
[Doc] Add clarification for defining multi-bit global tile ports
2021-01-09 20:00:16 -07:00
2324edc522
[Doc] Update documentation for upgraded tile annotation
2021-01-09 18:55:16 -07:00
226f6b8d6d
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
2021-01-04 18:30:04 -07:00
406edeec89
[Doc] Typo fix
2020-12-04 15:07:02 -07:00
4fe190fa7e
[Doc] Bug fix in LUT circuit model documentation
2020-12-04 14:44:27 -07:00
8350b0f911
[Doc] Update documentation about default value definition in tile annotation
2020-12-02 17:08:34 -07:00
cc0114459a
[Doc] Enrich examples for LUT circuit models
2020-11-26 13:03:12 -07:00
62e804215b
[Doc] Add svg figures for LUT examples
2020-11-26 12:35:39 -07:00
b857135f4e
[Doc] Add clarification about which cells are applicable for signal initialization
2020-11-23 15:19:15 -07:00
2b9a97729e
[Doc] Update documentation to clarify the port sequence for MUX2 and pass-gate logic circuit models
2020-11-23 15:09:47 -07:00
fd0e6814ea
[Doc] Update documentation about the pre-processing flags
2020-11-22 20:33:15 -07:00
f6126d1ed6
[Doc] Add illustrative example to diff between global ports definitions
2020-11-12 09:24:39 -07:00
bc43c876b0
[Doc] Update documentation for the rules in global port definition for tile ports
2020-11-11 14:10:11 -07:00
2c269c532a
[Doc] Update doc for the global port definition using physical tile port
2020-11-10 20:48:28 -07:00
056b7c0c79
[Doc] Update documentation about CCFF circuit model examples
2020-11-06 12:22:22 -07:00
849ecc7fc0
[Doc] Add notes for using the is_data_io syntax
2020-11-05 09:30:19 -07:00
9bce2f3818
[Doc] Update documentation for new XML syntax "is_data_io"
2020-11-05 09:28:46 -07:00
be7f7592ae
[Doc] Update documentation about don't care bit in frame address
2020-10-30 22:13:28 -06:00
7e940980e1
[Doc] Update documentation about configuration regions for frame-based protocol
2020-10-30 21:52:01 -06:00
c2c384e24b
[Doc] update documentation about memory bank definition
2020-10-29 17:04:25 -06:00
3aeea724de
[Documentation] Update for new options in fpga-verilog
2020-10-12 12:36:24 -06:00
ccaa697e5a
[Documentation] Add links to technical features to examples
2020-10-10 22:40:37 -06:00
56ab63d939
[Documentation] Fix format in table
2020-10-06 12:02:15 -06:00
113708c68f
[Documentation] Reorganization the overview part by adding technical highlights
2020-10-06 11:56:10 -06:00
67300af987
[Documentation] Update motivation with new set of figures
2020-09-29 16:52:16 -06:00
639d57016b
[Documentation] Update documentation about the multi-region configuration
2020-09-29 15:55:42 -06:00
462886fb5f
[Documentation] Update documentation for the multiple region support on configuration chain
2020-09-29 14:02:03 -06:00
94a1324f05
[Documentation] Remove deprecated XML syntax
2020-09-26 14:31:57 -06:00
f57fd273af
[Documentation] Update documentation for smart fast configuration
2020-09-23 21:28:06 -06:00
3d234d840b
[Documentation] Update documentation for the edge triggered attribute
2020-09-23 20:31:11 -06:00
7a2502ddf9
[documentation] add more guidelines about the vpr-openfpga architecture annotation
2020-09-02 22:47:14 -06:00
ac8e937a50
[Documentation] Update for default circuit model rules
2020-08-23 14:08:38 -06:00
tangxifan
AurelienAlacchi
ganeshgore