tangxifan
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0b49c22682
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[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
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2021-04-18 16:11:11 -06:00 |
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tangxifan
|
6550ea3dfa
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[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
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2021-04-18 12:02:49 -06:00 |
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tangxifan
|
6e9b24f9bf
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[Tool] Patch the invalid pin constraint net name
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2021-04-17 19:56:30 -06:00 |
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tangxifan
|
d95a1e2776
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[Tool] Encapulate search function in PinConstraint data structure
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2021-04-17 17:31:55 -06:00 |
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tangxifan
|
d877a02534
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
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tangxifan
|
85640a7403
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[Tool] Extend bitstream setting to support mode bits overload from eblif file
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2021-03-10 20:45:48 -07:00 |
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tangxifan
|
e34380a654
|
Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
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tangxifan
|
73461971d2
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[Tool] Bug fix for printing single-bit ports in Verilog netlists
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2021-02-28 16:12:57 -07:00 |
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tangxifan
|
7a5dd1bc02
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[Tools] Patch circuit library for dummy circuit models without any ports
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2021-02-24 10:36:48 -07:00 |
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tangxifan
|
b2984b46ee
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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
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2021-02-09 21:15:57 -07:00 |
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tangxifan
|
faabdab815
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[Tool] Remove redundant tab in bitstream setting writer
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2021-02-01 18:04:21 -07:00 |
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tangxifan
|
d5b1cc5ec7
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[Tool] Bug fix in parser for bitstream settings
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2021-02-01 18:01:42 -07:00 |
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tangxifan
|
f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
|
3b7762ef85
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[Lib] Now try to call undefined command will cause a error code to return
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2021-01-24 17:44:51 -07:00 |
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tangxifan
|
a8158322ef
|
[Tool] Bug fix in setting command execution status in OpenFPGA shell
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2021-01-24 17:25:03 -07:00 |
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tangxifan
|
fd0e73a9bb
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[Tool] Enhance return code for openfpga shell
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2021-01-24 14:48:27 -07:00 |
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tangxifan
|
8cac3291cb
|
[Tool] Add batch mode to openfpga shell execution
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2021-01-24 14:33:58 -07:00 |
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tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
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tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
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tangxifan
|
ecd955124b
|
[Lib] Add libpcf to CMakelist and bug fix
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2021-01-19 15:51:14 -07:00 |
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tangxifan
|
52ac7826eb
|
[Lib] Add a library of parser/writer for pin constraint file (PCF)
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2021-01-19 15:45:45 -07:00 |
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tangxifan
|
ea9d6bfe91
|
[Flow] Update the design constraint file to follow bug fix in parser
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2021-01-17 10:41:01 -07:00 |
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tangxifan
|
113119bd8e
|
[Lib] Fix the bug in repack design constraint parser
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2021-01-17 10:39:55 -07:00 |
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tangxifan
|
2efe513122
|
[Tool] Now repack consider design constraints; test pending
|
2021-01-16 21:57:17 -07:00 |
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tangxifan
|
d0e05b3575
|
[Lib] Now use pb_type in design constraints instead of physical tiles
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2021-01-16 21:35:43 -07:00 |
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tangxifan
|
b86adabe69
|
[Lib] Remove unused data storage from repack design constraints
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2021-01-16 21:14:52 -07:00 |
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tangxifan
|
706e84bb62
|
[Lib] Bug fix in testing program
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2021-01-16 18:15:56 -07:00 |
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tangxifan
|
67c54c4d3b
|
[Lib] Bug fix in the repack design constraint lib
|
2021-01-16 17:34:22 -07:00 |
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tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
|
2021-01-16 17:20:59 -07:00 |
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tangxifan
|
9d80f1ab39
|
[Lib] Add test program to the library of repack design constraints
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2021-01-16 17:18:42 -07:00 |
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tangxifan
|
03b5bcc244
|
[Lib] Add XML writer for repack design constraints
|
2021-01-16 17:15:31 -07:00 |
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tangxifan
|
2a7601fb7e
|
[Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints
|
2021-01-16 17:14:51 -07:00 |
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tangxifan
|
f1bfa2ef8c
|
[Lib] Add XML parser for repack design constraints
|
2021-01-16 17:03:01 -07:00 |
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tangxifan
|
8be12b6e82
|
[Lib] Add example design constraint file
|
2021-01-16 16:36:10 -07:00 |
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tangxifan
|
a926c74ae5
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[Lib] Add CMake script to compile the repack design constraint library
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2021-01-16 16:35:46 -07:00 |
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tangxifan
|
b57dc7b898
|
[Lib] Add repack design constraint library
|
2021-01-16 16:35:13 -07:00 |
|
tangxifan
|
b8e4675a3a
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[Tool] Add missing file
|
2021-01-15 14:48:19 -07:00 |
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tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
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tangxifan
|
4124777948
|
[Tool] Set (x,y) to be optional XML syntax in tile annotation
|
2021-01-09 18:56:41 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
|
cb34be0dc0
|
[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
|
2021-01-04 15:13:54 -07:00 |
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tangxifan
|
d195b9e32c
|
[Tool] Bug fix in XML syntax to define default values for a global tile port
|
2020-12-02 17:03:48 -07:00 |
|
tangxifan
|
e959821813
|
[Tool] Enhance internal check functions for tile annotation
|
2020-11-11 13:59:24 -07:00 |
|
tangxifan
|
4dc0fb81c5
|
[Tool] Bug fix for clang compilation error
|
2020-11-10 20:32:58 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
67af145455
|
[Tool] Add XML writer for tile annotation
|
2020-11-10 14:51:46 -07:00 |
|
tangxifan
|
6fbdbe68ae
|
[Tool] Add tile annotation parser
|
2020-11-10 14:32:24 -07:00 |
|
tangxifan
|
0a273ffab6
|
[Tool] Bug fix in the tight requirements on CCFF circuit model
|
2020-11-06 11:16:46 -07:00 |