bbleaptrot
|
858bb2f21e
|
fix mistake in first line of page
|
2021-06-16 12:45:04 -06:00 |
|
bbleaptrot
|
624e9f3bb7
|
Update notation at top to match pages in doc
|
2021-06-16 12:44:01 -06:00 |
|
bbleaptrot
|
ece6e92f06
|
Add video at top of page
|
2021-06-16 12:29:17 -06:00 |
|
bbleaptrot
|
7a303463c3
|
Update shell_shortcuts.rst
Update grammar. <_openfpga_task_args> no longer works
|
2021-06-14 15:34:13 -06:00 |
|
bbleaptrot
|
5e8b5d641f
|
Update compile.rst
update grammar
|
2021-06-14 14:51:19 -06:00 |
|
bbleaptrot
|
1a2ced678e
|
Update tech_highlights.rst
Update grammar and add link to standard_cell_library tutorial
|
2021-06-14 14:34:12 -06:00 |
|
bbleaptrot
|
d0549f10b3
|
Make a :ref: for tutorial
|
2021-06-14 14:28:21 -06:00 |
|
bbleaptrot
|
dc13325639
|
Update motivation.rst
Fixing grammar and spacing
|
2021-06-14 13:44:20 -06:00 |
|
bbleaptrot
|
986ea492f6
|
Fix grammar line 38: lookup table ->Look-Up Table
|
2021-04-19 14:16:40 -06:00 |
tangxifan
|
2ff3dc0a0f
|
Merge branch 'master' into tutorials
|
2021-04-19 11:35:18 -06:00 |
|
bbleaptrot
|
bc6e9746c2
|
Fix more grammar mistakes
|
2021-04-19 09:48:42 -06:00 |
|
bbleaptrot
|
8431337f39
|
Fix grammar errors in fig captions and elsewhere
|
2021-04-19 09:36:13 -06:00 |
|
bbleaptrot
|
86c856d35a
|
Fix reference links
|
2021-04-19 09:25:54 -06:00 |
|
bbleaptrot
|
cd6beb5789
|
Add one more link to fabric_netlists
|
2021-04-19 09:14:47 -06:00 |
|
bbleaptrot
|
f8810940c3
|
Update links
|
2021-04-19 09:10:17 -06:00 |
|
bbleaptrot
|
fcb7ee3283
|
Update to properly reference fabric netlist page
|
2021-04-19 09:05:30 -06:00 |
|
bbleaptrot
|
5010fb1e7f
|
Update hyperlinks
|
2021-04-19 08:52:05 -06:00 |
|
bbleaptrot
|
291638ee0f
|
Trying to resolve hyperlink to right location
|
2021-04-19 08:45:02 -06:00 |
|
bbleaptrot
|
beed1ce31e
|
replace hyperlink with more stable :ref: link
|
2021-04-19 08:38:09 -06:00 |
|
tangxifan
|
e85402eaaa
|
Merge pull request #293 from lnis-uofu/dff_techmap
Enable correct reset stimuli in testbench generators
|
2021-04-18 17:15:28 -06:00 |
|
tangxifan
|
0b49c22682
|
[Tool] Now Verilog testbench generator support adding dedicated stimuli for reset signals from benchmarks
|
2021-04-18 16:11:11 -06:00 |
|
tangxifan
|
82dd09a180
|
Merge branch 'master' into dff_techmap
|
2021-04-18 12:09:52 -06:00 |
|
tangxifan
|
6550ea3dfa
|
[Tool] Rework pin constarint API to avoid expose raw data to judge for developers
|
2021-04-18 12:02:49 -06:00 |
|
tangxifan
|
0e65442afd
|
Merge pull request #292 from lnis-uofu/dff_techmap
Verilog testbench generator now accepts pin constraints on non-clock global ports
|
2021-04-17 23:02:35 -06:00 |
|
tangxifan
|
6e9b24f9bf
|
[Tool] Patch the invalid pin constraint net name
|
2021-04-17 19:56:30 -06:00 |
|
tangxifan
|
253422e7b7
|
[Tool] Bugfix due to refactoring
|
2021-04-17 19:27:03 -06:00 |
|
tangxifan
|
02ca51d84b
|
[Tool] Reorganize functions in full testbench generator to avoid big-chunk codes
|
2021-04-17 17:45:50 -06:00 |
|
tangxifan
|
d95a1e2776
|
[Tool] Encapulate search function in PinConstraint data structure
|
2021-04-17 17:31:55 -06:00 |
|
tangxifan
|
da619fabe7
|
[Tool] FPGA-Verilog testbench generator accepts pin constraints in full testbench
|
2021-04-17 17:19:34 -06:00 |
|
tangxifan
|
03a709dce9
|
Merge branch 'master' into dff_techmap
|
2021-04-17 16:20:55 -06:00 |
|
tangxifan
|
6e1b58f8a6
|
[Tool] Update FPGA-Verilog testbench generator to accept pin constraints to non-clock global ports
|
2021-04-17 15:05:22 -06:00 |
|
tangxifan
|
7018073e28
|
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
|
2021-04-17 15:04:51 -06:00 |
|
tangxifan
|
da95da933b
|
[Test] Add pin constraint file to map reset to correct FPGA pins
|
2021-04-17 15:04:26 -06:00 |
|
tangxifan
|
64b2700979
|
Merge branch 'master' into tutorials
|
2021-04-17 10:19:30 -06:00 |
|
tangxifan
|
8c5eb5e1d7
|
Merge pull request #291 from lnis-uofu/dff_techmap
Support DFF with asynchronous reset in tech mapping
|
2021-04-16 21:52:22 -06:00 |
|
tangxifan
|
e3dafe99da
|
[Arch] Revert to old version arch due to editing by mistake
|
2021-04-16 20:58:32 -06:00 |
|
tangxifan
|
c020333512
|
Merge branch 'master' into dff_techmap
|
2021-04-16 20:54:28 -06:00 |
|
tangxifan
|
7172fc9ea1
|
[Test] Patch test for architecture using asynchronous DFFs
|
2021-04-16 20:48:37 -06:00 |
|
tangxifan
|
0a15f366cb
|
[HDL] Patch dff models used in yosys tech map
|
2021-04-16 20:48:15 -06:00 |
|
tangxifan
|
16e02ef485
|
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
|
2021-04-16 20:47:39 -06:00 |
|
tangxifan
|
1c2f91b7e6
|
[Script] Patch yosys script with dff tech map
|
2021-04-16 20:47:18 -06:00 |
|
tangxifan
|
2666726f36
|
[Script] Remove clock routing from example openfpga shell script without ace
|
2021-04-16 20:46:49 -06:00 |
|
tangxifan
|
23d08757cf
|
[Script] Add example script without using ACE2
|
2021-04-16 20:20:10 -06:00 |
|
tangxifan
|
bbdc0e53af
|
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
|
2021-04-16 20:14:48 -06:00 |
|
tangxifan
|
b11d03f9c5
|
[Test] Deploy new test to CI
|
2021-04-16 20:01:40 -06:00 |
|
tangxifan
|
93be81abe1
|
[Test] Add test case for architecture using DFF with reset
|
2021-04-16 20:00:48 -06:00 |
|
tangxifan
|
5414a6a3da
|
[Script] Add yosys script with custom DFF tech mapping
|
2021-04-16 20:00:30 -06:00 |
|
tangxifan
|
4239bb4e68
|
[Arch] Patch architecture files using multi-mode DFFs
|
2021-04-16 19:59:55 -06:00 |
|
tangxifan
|
f2f7f010ea
|
[Arch] Add new architectures using DFF with reset in VPR
|
2021-04-16 19:26:18 -06:00 |
|
tangxifan
|
64294ae4eb
|
[Doc] Update README for architecture files due to new architecture features
|
2021-04-16 19:25:54 -06:00 |