tangxifan
|
18257b3fa1
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[Engine] Update BL/WL port addition for the top-level module in fabric generator
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2021-09-24 11:07:58 -07:00 |
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tangxifan
|
8c281a22b0
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[Engine] Add check codes to validate circuit models for BL/WL protocols
|
2021-09-23 14:39:16 -07:00 |
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tangxifan
|
962acda810
|
[Engine] Bug fix in fabric key generation when computing configurable children
|
2021-09-22 11:09:46 -07:00 |
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tangxifan
|
36a4da863c
|
[Engine] Support WLR port in OpenFPGA architecture file and fabric generator
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2021-09-20 16:05:36 -07:00 |
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tangxifan
|
b787c4e100
|
[Engine] Register QL memory bank as a legal protocol
|
2021-09-09 15:06:51 -07:00 |
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tangxifan
|
6f09f5f7ad
|
[FPGA-Bitstream] Upgrade bitstream generator to support QL memory bank
|
2021-09-05 21:25:58 -07:00 |
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tangxifan
|
b83eef47b4
|
[Tool] Bug fix for testbench generation without self checking codes
|
2021-06-29 16:27:29 -06:00 |
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tangxifan
|
6a260cadbf
|
[Tool] Remove option ``--no_self_checking`` option but use the existing option ``--reference_benchmark_path`` to achieve the same purpose
|
2021-06-29 15:42:23 -06:00 |
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tangxifan
|
7ac7de789e
|
[Tool] Add a new option ``--no_self_checking`` so that users can output a simple testbench without self checking codes
|
2021-06-29 15:26:40 -06:00 |
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tangxifan
|
991062e9bf
|
[Tool] Bug fix
|
2021-06-25 15:22:42 -06:00 |
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tangxifan
|
90163fab6c
|
[Tool] Replace option '--support_icarus_simulator' with a new one '--preload_bitstream <string>'
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2021-06-25 15:06:07 -06:00 |
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tangxifan
|
2bb514c51a
|
[Tool] Support time unit in writing simulation information file
|
2021-06-25 10:33:29 -06:00 |
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tangxifan
|
bcc16d732c
|
[Tool] Add new option 'testbench_type' so that simulation task can write different information for different testbenches
|
2021-06-25 10:10:16 -06:00 |
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tangxifan
|
5364d8104f
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[Tool] Add signal_init option to preconfigured fabric wrapper writer
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2021-06-24 17:07:41 -06:00 |
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tangxifan
|
fed975c52a
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[Tool] Add postfix removal support in write_io_mapping command
|
2021-06-18 16:13:50 -06:00 |
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tangxifan
|
d9d57aad42
|
[Tool] Added default net type options to verilog testbench generator command
|
2021-06-14 11:37:49 -06:00 |
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tangxifan
|
7ade48343c
|
[Tool] Deprecate command 'write_verilog_testbench'
|
2021-06-09 17:06:01 -06:00 |
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tangxifan
|
2299ce3157
|
[Tool] Preconfigured testbench writer now supports icarus simulator
|
2021-06-09 13:49:25 -06:00 |
|
tangxifan
|
3bc8e760db
|
[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
|
2021-06-09 11:14:45 -06:00 |
|
tangxifan
|
89fb672631
|
[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
|
2021-06-09 10:49:00 -06:00 |
|
tangxifan
|
97396eda2b
|
[Tool] Add a new command 'write_simulation_task_info'
|
2021-06-08 22:10:02 -06:00 |
|
tangxifan
|
d2275b971d
|
[Tool] Add a new command 'write_preconfigured_testbench'
|
2021-06-08 21:53:51 -06:00 |
|
tangxifan
|
8db19c7af9
|
[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
|
2021-06-08 21:28:16 -06:00 |
|
tangxifan
|
061f832429
|
[Tool] Enable fast configuration when writing fabric bitstream
|
2021-06-04 16:23:40 -06:00 |
|
tangxifan
|
81048d3698
|
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
|
2021-06-04 11:26:39 -06:00 |
|
tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
|
2021-06-03 15:41:11 -06:00 |
|
tangxifan
|
c4ecc9ee7c
|
[Tool] Patch data type of report bitstream distribution command-line option
|
2021-05-07 11:44:01 -06:00 |
|
tangxifan
|
db9bb9124e
|
[Tool] Add report bitstream distribution command to openfpga shell
|
2021-05-07 11:41:25 -06:00 |
|
tangxifan
|
43c1e052ef
|
[Tool] Add a writer to output I/O mapping information to XML files
|
2021-04-27 14:30:16 -06:00 |
|
tangxifan
|
56948244bc
|
[Tool] Patch a critical bug in pb pin fixup
|
2021-04-22 16:19:54 -06:00 |
|
tangxifan
|
0aec30bac6
|
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
|
2021-04-19 15:53:33 -06:00 |
|
tangxifan
|
c8d41b4e69
|
[Tool] Change routing module port naming to include architecture port names
|
2021-03-14 19:35:49 -06:00 |
|
tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
|
2021-03-13 20:23:08 -07:00 |
|
tangxifan
|
2c5634ee76
|
[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
|
tangxifan
|
15e26a5602
|
[Tool] Support default_net_type Verilog syntex in fabric generator
|
2021-02-28 11:57:40 -07:00 |
|
tangxifan
|
aae03482f5
|
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
|
2021-02-18 19:37:17 -07:00 |
|
tangxifan
|
0c409b5bcc
|
[Tool] Add bitstream annotation support
|
2021-02-01 20:49:36 -07:00 |
|
tangxifan
|
f102e84497
|
[Tool] Add bitstream setting file to openfpga library
|
2021-02-01 17:43:46 -07:00 |
|
tangxifan
|
4b77a3a574
|
[Tool] Now activity file is not a manadatory input of openfpga tools
|
2021-01-29 11:33:40 -07:00 |
|
tangxifan
|
d9fda31a9f
|
[Tool] Add --version to openfpga shell option and a command to openfpga shell
|
2021-01-27 16:03:46 -07:00 |
|
tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
bb8e7e25c2
|
[Tool] Start deploying design constraints in repack engine
|
2021-01-16 21:27:12 -07:00 |
|
tangxifan
|
fa67517349
|
[Tool] Add repack design constraints to openfpga command 'repack'
|
2021-01-16 18:49:34 -07:00 |
|
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
|
tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
|
tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |