tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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6f133bd009
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bug fix in packable mode support
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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e089b0ef22
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use constant string for inverted port naming
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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c2a81c76e1
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update doc for new options
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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8915d10d27
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add verbose output option to configure port disable timing writer
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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6177921d4c
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bug fixed in configure port disable timing. Now we disable the right ports of LUTs
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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f52b5d5b4c
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use error code in read_arch command
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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e9ceedb01b
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use constant openfpga context in SDC generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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910be3cadb
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massively deploy disable_timing for configure ports in CI
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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067d09f954
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bug fix for configure port disable_timing writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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f4dd882f0f
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documentation updated for new command
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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ae9f1fbd90
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critical bug fixed in the disable MUX output
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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99751b84f5
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bug fix in configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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df9cf32b49
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update documenation for configuration chain writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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a41c8dbcb3
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change to use default sphinx build version
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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02e86c565a
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bug fix in configuration chain SDC writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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4c0953415b
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add configuration chain sdc writer
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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dad99d13a2
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bug fixed in SDC timing writer for primitive pb_type
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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8d2360a710
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simplify include_netlist.v
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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05d276097e
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critical bug fixed in openfpga shell so that our command parse results should be reset each time before parsing a line
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b8a79c563d
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bug fix in the SDC port generation
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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84d24ad075
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bug fix in pnr sdc grid writer for module paths in hierarchical view
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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99fa51cb49
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bug fixed in the SDC CB hierarchy writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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10e1a4b2fe
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format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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cc6d988872
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bug fix in grid SDC generator
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b167c85980
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fully expand grid hierarchy in SDC writer
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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55518f4cec
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minor fix in the sdc hierarchy writer for grids
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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b57a90a6ca
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add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
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2020-06-11 19:31:05 -06:00 |
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Xifan Tang
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24934aff86
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update documentation on the depth option for fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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5a8c05378e
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add --depth option to fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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d9dc7160a7
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minor fix on the hierarchy writer in SDC generator
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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752470c2da
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update documentation on write hierarchy command and options
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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17c254a370
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add missing file to follow up the previous commit
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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c651df6421
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add hierarchy writer to SDC generator
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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1943929353
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add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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6aff33dd35
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add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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0985c720e9
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remove regexp in SDC generation.
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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98fbcb5410
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add time unit test for SDC generation to CI
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2020-06-11 19:31:04 -06:00 |
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Xifan Tang
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ac378febef
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update doc about time units in SDC generator
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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8726c618eb
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add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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47f040822f
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deploy the tests to CI
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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4083fae41a
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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2fbf9c2cfc
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change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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0e44cf3ea3
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now SDC to disable routing multiplexer outputs can use wildcards
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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609115e51f
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now hierarchical SDC generation is applicable to CB timing constraints
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2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
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d18e924a89
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Update documentation on new fpga_sdc option
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7e82c23f52
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now add SDC generator supports both hierarchical and flatten in writing timing constraints
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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7503c58fb2
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small fix on SDC generator for SB which do not exist in FPGA
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2020-06-11 19:31:02 -06:00 |