Commit Graph

282 Commits

Author SHA1 Message Date
tangxifan 4c36b384d0 [doc] add new syntax 2024-11-26 17:26:30 -08:00
tangxifan 5a67d5dad1 [doc] add new syntax 2024-11-25 16:21:34 -08:00
Lin 75710f8c8a add warning in doc 2024-11-01 10:54:58 +08:00
Lin 539e37118a add option reduce error to warning 2024-10-31 10:47:26 +08:00
tangxifan af09120a52 [doc] update fig 2024-09-21 13:35:42 -07:00
tangxifan 26cda624d3 [doc] add new syntax about clock network 2024-09-21 13:31:30 -07:00
tangxifan 4905e694ab [doc] typo 2024-09-18 21:59:06 -07:00
tangxifan 1789ce06c4 [doc] update new syntax with example 2024-09-18 17:55:05 -07:00
Jingrong Lin b5452b7a3c
Merge branch 'master' into preloading_clean 2024-09-14 10:54:14 +08:00
Lin 423e15289c add link to command doc, valid now 2024-09-12 13:47:10 +08:00
Lin 52f5cf0399 add link to command doc 2024-09-12 13:36:06 +08:00
Victor e5b3f5d90c add link to file format description page 2024-09-12 12:48:00 +08:00
Lin e6c43ec9ad add command doc 2024-09-12 11:41:52 +08:00
Victor 7f88e97514 refine doc format 2024-09-12 10:33:06 +08:00
Victor 22da608e05 add ident 2024-09-12 09:58:13 +08:00
Victor 65e38e5f91 update document format 2024-09-11 19:27:03 +08:00
Lin 27db6d2496 modified unique_block.rst 2024-09-11 18:28:32 +08:00
Lin 172260e2fb modified index.rst 2024-09-11 18:17:45 +08:00
Jingrong Lin 77b188060b
Merge branch 'master' into preloading_clean 2024-09-11 11:08:49 +08:00
victorzh001 04a60ca4b5
Merge branch 'master' into victor_OpenFPGA_dbg 2024-09-10 11:01:47 +08:00
Victor 3ea830e168 Add the reference_file to the index.rst 2024-09-10 10:46:15 +08:00
tangxifan 3b1f51b9d9 [doc] add new options 2024-09-09 13:46:58 -07:00
Victor 8d97ebd980 Add more test cases and update documentation about the YAML file format of this command 2024-09-09 17:49:10 +08:00
Victor 7bacc781d0 update code according to code review comments 2024-09-06 15:39:08 +08:00
Jingrong Lin 263eb6b7fb
Update unique_blocks.rst 2024-09-04 15:14:41 +08:00
Lin a70582c6c4 preload document copied 2024-09-04 14:45:41 +08:00
tangxifan e7ab7a61f1 [doc] update to use tile name and index when defining clock taps 2024-08-09 18:09:12 -07:00
tangxifan 85c9bdc6f9 [doc] add new format 2024-08-06 17:28:03 -07:00
tangxifan c11a2c7381 [doc] format to resolve latexpdf build errors; now local build passes 2024-08-03 15:03:14 -07:00
chungshien-chai 22d7df5ffb Update doc 2024-07-28 02:40:24 -07:00
chungshien-chai cbe9a46f95 Format and update doc 2024-07-28 00:02:20 -07:00
chungshien-chai 0ff0c3445e Update doc 2024-07-26 13:43:31 -07:00
tangxifan 0c99fcf6f4 [doc] format 2024-07-10 15:07:57 -07:00
tangxifan a390aad0b8 [doc] add new syntax 2024-07-10 15:07:16 -07:00
tangxifan f42884304a [doc] update clock network details 2024-07-09 11:40:41 -07:00
tangxifan bf484dbc70 [doc] add perimeter cb examples on prog clk network 2024-07-08 21:25:12 -07:00
tangxifan 229adebe07 [doc] new option to write_fabric_verilog 2024-07-08 21:06:12 -07:00
tangxifan 8a5c33b1d6 [doc] new option for perimeter cb 2024-07-08 19:01:16 -07:00
tangxifan 4da5150a26 [doc] update for bottom-left tile organization 2024-07-07 14:20:26 -07:00
tangxifan 91f8bb5841 [doc] update figures for ecb 2024-07-07 13:40:01 -07:00
tangxifan e3a258a5ab [doc] typo 2024-07-02 19:31:45 -07:00
tangxifan ec7ca1add1 [doc] add example to example clock network 2024-07-01 21:41:33 -07:00
tangxifan 18e2b994ac [doc] update syntax on clock network file 2024-06-30 22:56:31 -07:00
tangxifan 1094af9f73 [doc] add new options to route clock graph 2024-06-28 12:38:40 -07:00
tangxifan 3fb891094b [doc] add new syntax 2024-06-27 11:02:37 -07:00
tangxifan ec1ad94d4a [doc] add syntax about internal drivers 2024-06-25 13:06:47 -07:00
tangxifan 253e3e0cba [doc] add new syntax for clock network 2024-06-23 17:43:38 -07:00
tangxifan b491ba03b7 [doc] typo 2024-05-29 10:33:39 -07:00
tangxifan 391b768b3a [doc] syntax 2024-05-21 11:14:12 -07:00
tangxifan 4c6b923b74 [doc] add a figure about ecb 2024-05-21 11:03:58 -07:00