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[doc] typo

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tangxifan 2024-07-02 19:31:45 -07:00
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docs/source/manual/file_formats/clock_network.rst
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@ -39,7 +39,7 @@ Using the clock network description language, users can define multiple clock ne
.. _fig_prog_clock_network_example_2x2:
.. figure:: figures/prog_clock_network_example_2x2.png
.. figure:: figures/prog_clk_network_example_2x2.png
:width: 100%
:alt: An example of programmable clock network considering a 2x2 FPGA fabric