[doc] update syntax on clock network file

docs/source/manual/arch_lang/annotate_vpr_arch.rst

@@ -79,6 +79,7 @@ For subtile port merge support (see an illustrative example in :numref:`fig_subt
 
 .. note:: When defined, the given port of all the subtiles of a tile will be merged into one port. For example, a tile consists of 8 subtile ``A`` and 6 subtile ``B`` and all the subtiles have a port ``clk``, in the FPGA fabric, all the ``clk`` of the subtiles ``A`` and ``B`` will be wired to a common port ``clk`` at tile level.
 
+.. note:: Note that when a dedicated clock network is defined, the size of the global port will follow the ``global_port`` defined in the clock network description file (See details in :ref:`file_formats_clock_network`)
 
 .. note:: When merged, the port will have a default side of ``TOP`` and index of ``0`` on all the attributes, such as width, height etc.
 
@@ -99,6 +100,8 @@ For global port support:
 
 - ``clock_arch_tree_name="<string>"`` defines the name of the programmable clock network, which the global port will drive. The name of the programmable clock network must be a valid name (See details in :ref:`file_formats_clock_network`)
 
+.. note:: ``clock_arch_tree_name`` is applicable to clock, reset and set signals.
+
 - ``is_reset="<bool>"`` define if the global port is a reset port at the top-level FPGA fabric. An operating reset port will be driven by proper signals in testbenches.
 
 - ``is_set="<bool>"`` define if the global port is a set port at the top-level FPGA fabric. An operating set port will be driven by proper signals in testbenches.

docs/source/manual/file_formats/clock_network.rst

@@ -23,7 +23,7 @@ Using the clock network description language, users can define multiple clock ne
 .. code-block:: xml
 
   <clock_networks default_segment="<string>" default_tap_switch="<string>" default_driver_switch="<string>"> 
-    <clock_network name="<string>" width="<int>"> 
+    <clock_network name="<string>" global_port="<int>"> 
       <spine name="<string>" start_x="<int>" start_y="<int>" end_x="<int>" end_y="<int>"> 
         <switch_point tap="<string>" x="<int>" y="<int>"> 
           <internal_driver tile_pin="<string>"/>
@@ -107,9 +107,9 @@ where the clock network is used to drive the global clock pin ``clk0`` in OpenFP
     </global_port>
   </tile_annotations>
 
-.. option:: width="<int>"
+.. option:: global_port="<int>"
 
-  The maximum number of clock pins that a clock network can drive.
+  Define the source port of the clock network. For example, ``clk[0:7]``. Note that the global port name should match the ``from_pin`` when defining the tap points (See details in :ref:`file_formats_clock_network_clock_tap_point`).
 
 .. _file_formats_clock_network_clock_spine: