0ca0d4dde4
[engine] add more printout info to help debugging vtr_upgrade branch
2022-09-17 10:41:37 -07:00
eab3580f79
[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity
2022-09-06 13:40:29 -07:00
2f84ce5955
[engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used
2022-09-06 11:48:21 -07:00
22f8d968cc
Ported fixes related to timing graph node remapping.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-07-21 10:29:58 +02:00
99eb13f135
vpr: netlist_writer: sdf: don't escape '[' and ']' chars for black boxes
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Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2022-07-15 15:14:10 +02:00
e220ddc9cd
Merge pull request #697 from antmicro/vpr-param-handling
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VPR: validate EBLIF parameters and fix them in verilog netlist writer
2022-06-30 11:06:57 -07:00
fb952fa487
Merge pull request #695 from lnis-uofu/win32-build
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Add support for (MinGW gcc) Windows build
2022-06-30 11:06:45 -07:00
26fce2511c
Merge pull request #700 from antmicro/vpr-merged-netlist-writer
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VPR: add second netlist writer for merged multi-bits ports
2022-06-30 11:04:58 -07:00
1677ac0ddb
fix count of ',' logic and clear stringstream for string to int conversion
2022-06-30 18:06:32 +05:30
46a3b9303f
vpr: add merged verilog netlist writer
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Signed-off-by: Paweł Czarnecki <pczarnecki@antmicro.com>
2022-06-30 14:22:30 +02:00
721ac99696
Correct handling of unconnected ports in output Verilog netlist...
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...so that outputs are not connected to constants.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-06-30 13:06:34 +02:00
782cdfd8e1
Added VPR commandline options that control unconnected port handling in the output Verilog netlist
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-06-30 13:06:34 +02:00
2609862580
Interpretation of EBLIF parameters and correct writing them to output Verilog netlist
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-06-30 10:20:34 +02:00
9fd8c02e13
header inclusions required for MinGW windows build
2022-06-29 07:03:38 +05:30
25c4c097ec
Refine code based on review feedback.
2022-06-10 18:13:23 -07:00
f8e049c73d
Fix tileable rr graph read/write issue.
2022-06-06 12:34:54 -07:00
b9e4977e7e
don't leave bus ports unconnected
2022-03-09 08:25:20 -08:00
9a49782158
fix output connected to X
2022-02-25 10:08:33 -08:00
1ff3267ade
bring changes related to post layout netlist and sdf generation for black box
2022-02-23 05:33:02 -08:00
025ee67bc7
[Engine] Clear up compiler warning in tileable rr_graph builder
2021-09-24 15:20:43 -07:00
cbd7105083
[Tool] Add illustrative comments to tileable rr_graph generator
2021-04-26 11:57:17 -06:00
880624e699
[Tool] Update comments in tileable rr_graph generator to be easier to be understood
2021-04-26 11:48:02 -06:00
3513966078
[Tool] Borrow a quick fix from the VPR pull request https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1656/files
2021-02-04 17:30:49 -07:00
95c9e19901
[Tool] Tileable rr_graph now accept I/Os in center grid
2020-12-04 17:43:35 -07:00
7206cafc0e
[Tool] Minor bug fix
2020-12-04 17:18:02 -07:00
29fd13a42a
[Tool] Relax restrictions on I/O location in tileable rr_graph builder
2020-12-04 17:07:01 -07:00
3d38e76c8f
Disabled printing segment ids for non-channel nodes.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-11-23 17:07:28 +01:00
b6728cf2d9
Added loading rr node segment indices
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2020-11-23 14:53:50 +01:00
801055b007
[OpenFPGA Tool] Bug Fix on the tileable RRG for multi segment
2020-09-22 12:47:02 -06:00
8041c90f12
bug fix in through channel support in tileable routing
2020-08-19 20:01:50 -06:00
f3ca1c0973
fix rr_graph on thru routing channel support
2020-08-19 17:28:25 -06:00
af1c7c6f29
start fixing the bug in thru channels
2020-08-19 12:18:35 -06:00
83e26adf90
add module usage types for future FPGA-SPICE development
2020-07-04 22:33:54 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
2ef083c49d
adapt SB module builder to use bus ports
2020-06-30 16:02:40 -06:00
b8bc74cc26
trying to fix the dependency problem of VPR GUI in openfpga shell
2020-06-11 19:31:15 -06:00
6f133bd009
bug fix in packable mode support
2020-06-11 19:31:07 -06:00
0c4904065f
reduce activity error to warning.
2020-04-22 17:36:02 -06:00
2342d7cdc6
minor tweak on the scan-chain support in VPR8 as well as architecture file
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Do NOT use pack patterns for the scan-chain. It will cause searching root chain in VPR8 to fail
Actually, we do not use scan-chain in mapping designs. Disable the pack pattern has no impact
2020-04-07 17:03:44 -06:00
13cd48c119
add support on packable/unpackable modes in VPR architecture
2020-04-06 16:07:49 -06:00
07e1979498
add architecture examples on wide memory blocks (width=2). tileable routing is working
2020-03-28 15:41:26 -06:00
5ce078fe60
minor fix on rr_graph.clear()
2020-03-27 11:26:14 -06:00
91a618466d
bug fixing for rr_graph.clear() function
2020-03-27 10:52:48 -06:00
3b3c39454b
update print_route() in VPR to show correct track_id when tileable routing is used
2020-03-25 17:55:28 -06:00
610c71671f
experimentally developing through channels inside multi-width and multi-height grids.
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Still debugging.
2020-03-24 16:47:45 -06:00
8a996ceae5
bug fixed in tileable routing when heterogeneous blocks are considered;
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VPR have special rules in checking the coordinates of SOURCE and SINK nodes,
which is very different from the OPIN and IPIN nodes
Show respect to it here.
2020-03-24 13:02:35 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
3958ac2494
fix bugs in flow manager on default compress routing problems
2020-03-22 15:26:15 -06:00
9a518e8bb6
bug fixed for tileable rr_graph builder for more 4x4 fabrics
2020-03-21 18:07:00 -06:00
63c4669dbb
fixed bug in the fast look-up for tileable rr_graph
2020-03-21 17:36:08 -06:00
tangxifan
Maciej Kurc
Pawel Czarnecki
coolbreeze413
taoli4rs
Tarachand Pagarani