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[engine] add more printout info to help debugging vtr_upgrade branch

This commit is contained in:
tangxifan 2022-09-17 10:41:37 -07:00
parent 30988d7072
commit 0ca0d4dde4
3 changed files with 27 additions and 9 deletions
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23
vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
View File

@ -25,7 +25,9 @@ namespace openfpga {
static
void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph,
const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
const DeviceGrid& grids) {
const DeviceGrid& grids,
size_t& num_edges_to_create) {
size_t edge_count = 0;
for (const RRNodeId& node : rr_graph.nodes()) {
/* Bypass all the non OPIN nodes */
if (OPIN != rr_graph.node_type(node)) {
@ -45,7 +47,10 @@ void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph,
/* add edges to the src_node */
rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]);
edge_count++;
}
VTR_LOG("Number edges to create source nodes: %d\n", edge_count);
num_edges_to_create += edge_count;
}
/************************************************************************
@ -55,7 +60,9 @@ void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph,
static
void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph,
const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
const DeviceGrid& grids) {
const DeviceGrid& grids,
size_t& num_edges_to_create) {
size_t edge_count = 0;
for (const RRNodeId& node : rr_graph.nodes()) {
/* Bypass all the non IPIN nodes */
if (IPIN != rr_graph.node_type(node)) {
@ -74,7 +81,10 @@ void build_rr_graph_edges_for_sink_nodes(RRGraph& rr_graph,
/* add edges to connect the IPIN node to SINK nodes */
rr_graph.create_edge(node, sink_node, rr_node_driver_switches[sink_node]);
edge_count++;
}
VTR_LOG("Number edges to create sink nodes: %d\n", edge_count);
num_edges_to_create += edge_count;
}
/************************************************************************
@ -97,10 +107,10 @@ void build_rr_graph_edges(RRGraph& rr_graph,
const e_switch_block_type& sb_type, const int& Fs,
const e_switch_block_type& sb_subtype, const int& subFs,
const bool& wire_opposite_side) {
size_t num_edges_to_create = 0;
/* Create edges for SOURCE and SINK nodes for a tileable rr_graph */
build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids);
build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids);
build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids, num_edges_to_create);
build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids, num_edges_to_create);
vtr::Point<size_t> gsb_range(grids.width() - 2, grids.height() - 2);
@ -132,10 +142,11 @@ void build_rr_graph_edges(RRGraph& rr_graph,
/* Build edges for a GSB */
build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb,
track2ipin_map, opin2track_map,
sb_conn, rr_node_driver_switches);
sb_conn, rr_node_driver_switches, num_edges_to_create);
/* Finish this GSB, go to the next*/
}
}
VTR_LOG("Number of edges to create: %ld\n", num_edges_to_create);
}
/************************************************************************

10
vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
View File

@ -925,8 +925,9 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
const t_track2pin_map& track2ipin_map,
const t_pin2track_map& opin2track_map,
const t_track2track_map& track2track_map,
const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches) {
const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
size_t& num_edges_to_create) {
size_t edge_count = 0;
/* Walk through each sides */
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
SideManager side_manager(side);
@ -940,6 +941,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
/* add edges to the opin_node */
for (const RRNodeId& track_node : opin2track_map[gsb_side][inode]) {
rr_graph.create_edge(opin_node, track_node, rr_node_driver_switches[track_node]);
edge_count++;
}
}
@ -954,6 +956,7 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode);
for (const RRNodeId& ipin_node : track2ipin_map[gsb_side][inode]) {
rr_graph.create_edge(chan_node, ipin_node, rr_node_driver_switches[ipin_node]);
edge_count++;
}
}
}
@ -963,9 +966,12 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
const RRNodeId& chan_node = rr_gsb.get_chan_node(gsb_side, inode);
for (const RRNodeId& track_node : track2track_map[gsb_side][inode]) {
rr_graph.create_edge(chan_node, track_node, rr_node_driver_switches[track_node]);
edge_count++;
}
}
}
VTR_LOG("Number of edges to create for gsb[%ld][%ld]: %ld\n", rr_gsb.get_x(), rr_gsb.get_y(), edge_count);
num_edges_to_create += edge_count;
}
/************************************************************************

3
vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.h
View File

@ -53,7 +53,8 @@ void build_edges_for_one_tileable_rr_gsb(RRGraph& rr_graph,
const t_track2pin_map& track2ipin_map,
const t_pin2track_map& opin2track_map,
const t_track2track_map& track2track_map,
const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches);
const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
size_t& num_edges_to_create);
t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
const RRGSB& rr_gsb,