tangxifan
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846ca26311
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[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
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2022-09-20 12:08:24 -07:00 |
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tangxifan
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40663f956c
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[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
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2022-09-19 21:55:15 -07:00 |
Ganesh Gore
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275cda081e
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[Bugfix] Typo
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2022-05-05 08:40:21 -06:00 |
|
Ganesh Gore
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e845b62322
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Update regession tasks
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2022-05-05 01:46:19 -06:00 |
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tangxifan
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d0fe8d96fa
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[Test] Update template scripts and assoicated test cases by offering more options
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2022-02-14 16:03:48 -08:00 |
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tangxifan
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70363effa4
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[Test] Add a new test to validate 8-bit counters using full testbenches
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2022-02-14 15:57:55 -08:00 |
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tangxifan
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7ef808cbe4
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[Test] Update pin constraints for different counter benchmarks
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2022-02-14 15:28:03 -08:00 |
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tangxifan
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570c1b10dc
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[Test] Add dedicated pin constraints for counter designs
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2022-02-14 13:54:48 -08:00 |
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tangxifan
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85011824e2
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[Test] Enable Verilog-to-Verification flow for counter8 benchmarks
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2022-02-14 13:15:55 -08:00 |
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tangxifan
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6630c17c23
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[Test] Use preconfigured testbench template to run counter8 tests
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2022-02-14 13:07:31 -08:00 |
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tangxifan
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da3f9ccb80
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[Test] Truncating counter designs in each task
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2022-02-14 12:22:19 -08:00 |
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tangxifan
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0268814fc6
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[Test] Splitting counter benchmarks into 2 categories; One has Verilog-to-Verification tests, while the other has only Verilog-to-Bitstream tests
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2022-02-14 12:20:56 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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397f2e71f1
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Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
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2022-01-19 20:43:26 +05:00 |
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Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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tangxifan
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7f999d03c6
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[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
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2021-10-30 18:05:39 -07:00 |
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tangxifan
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370e3fef83
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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
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2021-10-30 18:03:59 -07:00 |
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tangxifan
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a4cfc84930
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[Test] Bug fix
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2021-10-30 16:00:47 -07:00 |
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tangxifan
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64dcdaec61
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[Test] Update all the tasks that use counter benchmark
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2021-07-02 17:29:13 -06:00 |
ANDREW HARRIS POND
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006b54c4bc
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ready for merge
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2021-07-01 15:35:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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ANDREW HARRIS POND
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db9231c225
|
tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
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tangxifan
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477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
|
f06017581c
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[Test] Bug fix in counter micro benchmark tests
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2021-06-22 16:33:50 -06:00 |
|
tangxifan
|
760570d883
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[Test] Update counter test case for cover most counter HDL design
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2021-06-21 18:13:18 -06:00 |
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tangxifan
|
9c24a739be
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[Test] Added a MAC benchmark sweeping test
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2021-06-21 17:40:53 -06:00 |
Andrew Pond
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3cfc42cdf9
|
added testbench CI
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2021-06-15 14:16:31 -06:00 |
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tangxifan
|
784713e88a
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[Test] Add golden results for IWLS2005 as a simple QoR check
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2021-04-22 19:27:31 -06:00 |
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tangxifan
|
1dcb8e39a9
|
[Test] Unlock more IWLS'2005 benchmarks in testing
|
2021-04-22 09:23:33 -06:00 |
|
tangxifan
|
61a473e479
|
[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
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2021-04-21 22:56:19 -06:00 |
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tangxifan
|
3a5c26c6a1
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[Test] Update IWLS test by using new architecture and customize DFF techmap
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2021-04-21 19:51:25 -06:00 |
|
tangxifan
|
1566a5558a
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[Test] Add task configuration file for iwls2005
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2021-04-16 16:10:31 -06:00 |
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tangxifan
|
351dec5935
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[Test] Add QoR csv file for vtr benchmarks
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2021-03-23 11:15:02 -06:00 |
|
tangxifan
|
61eddb08de
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[Test] Update task configuration by commenting out high-runtime VTR benchmarks
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2021-03-22 14:42:42 -06:00 |
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tangxifan
|
4bfd0c0a02
|
[Test] Enable more VTR benchmark in testing
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2021-03-22 12:53:30 -06:00 |
|
tangxifan
|
cc10b10703
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[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
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2021-03-20 22:53:37 -06:00 |
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tangxifan
|
9a3aff274f
|
[Test] Use fix routing channel width to save runtime for VTR benchmarks
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2021-03-20 21:59:44 -06:00 |
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tangxifan
|
ca9a70fc88
|
[Test] Comment out benchmarks have problems in synthesis
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2021-03-20 21:29:21 -06:00 |
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tangxifan
|
125e94a6b3
|
[Test] Add full VTR benchmark (with most commented); ready for massive testing
|
2021-03-20 21:01:18 -06:00 |
|
tangxifan
|
f3792bc6f6
|
[Test] Update VTR benchmark test case to include DSP example benchmark
|
2021-03-20 18:09:19 -06:00 |
|
tangxifan
|
1976a8068f
|
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
|
2021-03-17 15:11:17 -06:00 |
|
tangxifan
|
9b6b2068ee
|
[Test] Move MCNC test to benchmark sweep test group
|
2021-02-22 10:18:34 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
tangxifan
|
a3eba8acbe
|
update task files using the new syntax on SHELL variables
|
2020-07-27 15:25:49 -06:00 |
|
tangxifan
|
1e6955aaa4
|
rename arch directory to be clear for its usage
|
2020-07-04 19:13:28 -06:00 |
|
tangxifan
|
f9a2bb0490
|
Reorganize task directory
|
2020-07-04 19:06:41 -06:00 |