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OpenFPGA
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4488 Commits

Author SHA1 Message Date
Lalit Sharma 756b64671b Fixing yosys checkout error 2021-11-12 02:33:25 -08:00
Lalit Sharma fe74c42252 Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure 2021-11-12 01:46:06 -08:00
Lalit Sharma 7b611601fc Bumping up changes to submodule yosys-plugins 2021-11-12 01:14:01 -08:00
coolbreeze413 840fa399c6 enable single counter test (fails, needs debug) 2021-11-09 21:36:33 +05:30
coolbreeze413 a823c3e143 remove clean step in build to avoid long compilation times 2021-11-04 10:19:25 +05:30
coolbreeze413 192eb1e655 correct yosys paths for CI 2021-11-04 09:11:57 +05:30
coolbreeze413 d2ce4579cf add yosys-symbiflow-plugins submodule 2021-11-04 07:54:44 +05:30
coolbreeze413 3fa373f8bc add plugins, set yosys install for plugin 2021-11-04 07:22:09 +05:30
ganeshgore a42342fa9e
Merge pull request #402 from lnis-uofu/yosys+verific_support 
Adding Yosys+Verific support.
 2021-11-02 15:22:48 -06:00
tangxifan f86b6960e2
Merge pull request #36 from RapidSilicon/upstream 
Upstream
 2021-11-01 10:39:13 -07:00
Aram Kostanyan a707226ba6 Added 'basic_tests/verific_test' test case into regression tests suite. 2021-11-01 18:33:33 +05:00
Aram Kostanyan b332a5a1b4 Added 'basic_tests/verific_test' test-case. 2021-11-01 18:20:57 +05:00
tangxifan ff264c00a2 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-31 11:51:34 -07:00
tangxifan 0d882f57b1
Merge branch 'master' into yosys+verific_support 2021-10-30 22:49:21 -07:00
tangxifan 4e50644ea8
Merge pull request #403 from lnis-uofu/yosyshq 
Use Yosys HQ v0.10 as a submodule
 2021-10-30 20:57:49 -07:00
tangxifan 0d14aa4cb8 [Flow] Add comments to clarify the limitations 2021-10-30 19:17:11 -07:00
tangxifan 7f999d03c6 [Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade 2021-10-30 18:05:39 -07:00
tangxifan 370e3fef83 [Test] Now use pre-configured testbench when verifying signal gen microbenchmarks 2021-10-30 18:03:59 -07:00
tangxifan 7455990ead [Flow] bug fix 2021-10-30 16:52:32 -07:00
tangxifan c8e9dfbeda [Test] bug fix 2021-10-30 16:50:57 -07:00
tangxifan 27b82d1473 [Flow] bug fix 2021-10-30 16:09:31 -07:00
tangxifan a4cfc84930 [Test] Bug fix 2021-10-30 16:00:47 -07:00
tangxifan 335347a74f [Test] Bug fix 2021-10-30 15:48:25 -07:00
tangxifan 6277234125 [Flow] bug fix in BRAM-oriented yosys scripts 2021-10-30 15:34:30 -07:00
tangxifan be47e78289 [Arch] Change arch for Sapone test 2021-10-30 15:23:19 -07:00
tangxifan e6cc3c4942 [Flow] Enable flatten for dff-related yosys scripts 2021-10-30 15:12:34 -07:00
tangxifan ad5cce0ae8 [Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals 2021-10-30 15:11:07 -07:00
tangxifan 8dea7e80e6 [Flow] Update yosys script to not use sdff and dffe 2021-10-30 14:56:54 -07:00
tangxifan 40d11a45d9 [Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade 2021-10-30 14:49:56 -07:00
tangxifan b7ad61227d [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:47:37 -07:00
tangxifan ec184ef532 [Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF 2021-10-30 14:46:12 -07:00
tangxifan 0b770f3330 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:36:43 -07:00
tangxifan 59a622a910 [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 14:34:37 -07:00
tangxifan 978c60e75b [Flow] Disable DFFE and SDFF in no-ff Yosys scripts 2021-10-30 13:29:38 -07:00
tangxifan 18bab18032 [Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release 2021-10-30 13:20:58 -07:00
tangxifan 16de60e943 [Test] Turn off ACE2 run in bitstream generation only flows 2021-10-30 12:31:14 -07:00
tangxifan 94328351be [Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts 2021-10-30 12:00:06 -07:00
tangxifan 91627abe12 [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided 2021-10-30 11:53:46 -07:00
tangxifan 0a449cc24c [HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected 2021-10-30 11:45:01 -07:00
tangxifan 9c06041ce4 [Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff` 2021-10-30 11:27:40 -07:00
tangxifan e8b3c68565 [Github] Now use YosysHQ v0.10 release as a submodule 2021-10-29 14:19:26 -07:00
tangxifan 104e177e37 [Git] Update yosys submodule: 2021-10-29 14:17:42 -07:00
tangxifan aece87b0c8 [Github] debugging 2021-10-29 14:15:16 -07:00
tangxifan 39fa050b3b [Github] debugging 2021-10-29 14:13:02 -07:00
tangxifan f2ce2e6126 [Github] debugging 2021-10-29 14:11:45 -07:00
tangxifan b213faaf81 [Git] Add YosysHQ as a submodule in the place of QuickLogic Yosys 2021-10-29 13:54:15 -07:00
Aram Kostanyan a355977420 Adding Yosys+Verific support. 2021-10-29 18:34:27 +05:00
tangxifan 83d859f60d
Merge pull request #34 from RapidSilicon/upstream 
Bring Upstream to Current Master
 2021-10-28 16:53:55 -07:00
tangxifan b8d5920529 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream 2021-10-28 15:45:58 -07:00
tangxifan ddf96fc23a
Merge pull request #397 from lnis-uofu/gg_ci_cd_dev 
Updated CI documentation
 2021-10-28 15:27:37 -07:00