tangxifan
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5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
|
6001da3a40
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[Arch] Bug fix in tileable I/O arch example
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2020-12-04 17:56:54 -07:00 |
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tangxifan
|
73aaa261d8
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[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
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2020-12-04 17:55:25 -07:00 |
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tangxifan
|
95c9e19901
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[Tool] Tileable rr_graph now accept I/Os in center grid
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2020-12-04 17:43:35 -07:00 |
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tangxifan
|
1d0bdcfeca
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[Arch] Simplify the grid layout modeling
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2020-12-04 17:38:44 -07:00 |
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tangxifan
|
7206cafc0e
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[Tool] Minor bug fix
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2020-12-04 17:18:02 -07:00 |
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tangxifan
|
1c3f625e41
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[Arch] Force empty tiles at corners for tileable I/O arch example
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2020-12-04 17:11:06 -07:00 |
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tangxifan
|
29fd13a42a
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[Tool] Relax restrictions on I/O location in tileable rr_graph builder
|
2020-12-04 17:07:01 -07:00 |
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tangxifan
|
0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
|
186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
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tangxifan
|
406edeec89
|
[Doc] Typo fix
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2020-12-04 15:07:02 -07:00 |
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tangxifan
|
4fe190fa7e
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
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tangxifan
|
4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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tangxifan
|
b661c39b04
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[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
|
2020-12-02 19:36:36 -07:00 |
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tangxifan
|
412fb5bb31
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[Arch] Bug fix due to valid default value parser
|
2020-12-02 17:51:50 -07:00 |
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tangxifan
|
8350b0f911
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[Doc] Update documentation about default value definition in tile annotation
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2020-12-02 17:08:34 -07:00 |
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tangxifan
|
d195b9e32c
|
[Tool] Bug fix in XML syntax to define default values for a global tile port
|
2020-12-02 17:03:48 -07:00 |
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tangxifan
|
290ff028cd
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[Test] Add global_tile_reset test case to CI
|
2020-11-30 18:12:47 -07:00 |
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tangxifan
|
179b0ce304
|
[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
|
2020-11-30 18:11:47 -07:00 |
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tangxifan
|
c7604ab94f
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[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
|
2020-11-30 18:02:00 -07:00 |
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tangxifan
|
ff53d2c375
|
[HDL] Add new Scan-chain DFF cell
|
2020-11-30 17:54:10 -07:00 |
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tangxifan
|
ad703ad85b
|
[HDL] Add new gpio cell with protection circuitry
|
2020-11-30 17:52:39 -07:00 |
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tangxifan
|
27a480b5f8
|
[Test] arch name fix in the test case
|
2020-11-30 17:45:54 -07:00 |
|
tangxifan
|
7a0a3398d4
|
[Arch] Add new architecture to test global reset ports defined thru tile ports
|
2020-11-30 17:43:41 -07:00 |
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tangxifan
|
a1d3b439d3
|
[Test] Add a new test case to define a global reset port from a global tile port
|
2020-11-30 17:19:12 -07:00 |
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tangxifan
|
fc79e83e44
|
[Doc] Update README with latest Github Action badge
|
2020-11-30 11:57:08 -07:00 |
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tangxifan
|
cc0114459a
|
[Doc] Enrich examples for LUT circuit models
|
2020-11-26 13:03:12 -07:00 |
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tangxifan
|
62e804215b
|
[Doc] Add svg figures for LUT examples
|
2020-11-26 12:35:39 -07:00 |
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tangxifan
|
dc5e2c99af
|
[Test] Add native fracturable LUT4 test to CI
|
2020-11-25 23:02:18 -07:00 |
|
tangxifan
|
3a708cff21
|
[Tool] Bug fix to enable nature fracturable LUT design
|
2020-11-25 23:01:18 -07:00 |
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tangxifan
|
a60bd4d14a
|
[Arch] Bug fix in nature fracturable architecture
|
2020-11-25 22:48:26 -07:00 |
|
tangxifan
|
b8559249dc
|
[Test] Bug fix in task configuration file
|
2020-11-25 22:23:27 -07:00 |
|
tangxifan
|
26e4db56ad
|
[Test] Add new test case for the native fracturable LUT4
|
2020-11-25 22:21:23 -07:00 |
|
tangxifan
|
17070c6405
|
[Doc] Update README in openfpga arch directory for native fracturable LUT design
|
2020-11-25 22:19:20 -07:00 |
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tangxifan
|
f6a667de58
|
[Arch] Add openfpga architecture using native fracturable LUT
|
2020-11-25 22:18:03 -07:00 |
|
tangxifan
|
eda671592e
|
[Doc] Update README about new keyword about fracturable LUT
|
2020-11-25 22:12:56 -07:00 |
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tangxifan
|
0f841aa6d1
|
[Arch] Add an example architecture using native fracturable LUT
|
2020-11-25 22:11:14 -07:00 |
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tangxifan
|
d2954f025f
|
Merge branch 'master' into dev
|
2020-11-24 20:08:44 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
e87f29784d
|
Merge pull request #133 from LNIS-Projects/github-actions-test
Use GitHub Actions as CI
|
2020-11-24 20:06:48 -07:00 |
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tangxifan
|
96a99fcb6b
|
[Test] Change to short build name and see if ccache is working or not
|
2020-11-24 18:58:06 -07:00 |
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tangxifan
|
df98c83d33
|
[Test] Keep trying the paths for ccache
|
2020-11-24 18:10:52 -07:00 |
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tangxifan
|
91709abe80
|
[Test] Try to get the correct path to github workspace
|
2020-11-24 18:00:59 -07:00 |
|
tangxifan
|
9f956502b7
|
[Test] keep fixing the path to ccache file
|
2020-11-24 17:56:08 -07:00 |
|
tangxifan
|
6b757e2dca
|
[Test] Bug fix in ccache path
|
2020-11-24 17:50:22 -07:00 |
|
tangxifan
|
0af1c0468e
|
[Test] Spot cache file and try to use it
|
2020-11-24 17:41:27 -07:00 |
|
tangxifan
|
df317271fd
|
[Test] Try to check if .ccache is in the build directory
|
2020-11-24 16:54:55 -07:00 |
|
tangxifan
|
c7d288c043
|
[Test] Try to new cache action version to see if problem is solved
|
2020-11-24 16:50:29 -07:00 |
|
tangxifan
|
cba07b6020
|
[Test] Now travis and github actions share the common regression test scripts
|
2020-11-24 15:58:09 -07:00 |
|
tangxifan
|
ab3c41715e
|
[Doc] Update badges for the github actions
|
2020-11-24 15:44:16 -07:00 |
|
tangxifan
|
ca593f23fc
|
[Test] Merge reg test to build tests on Github Actions
|
2020-11-24 15:32:45 -07:00 |