tangxifan
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0da92ad888
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[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
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2020-12-04 22:16:51 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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09fa83ddfc
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Merge pull request #147 from lnis-uofu/dev
Support I/O tiles in the center part of FPGA grid layout
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2020-12-04 19:30:31 -07:00 |
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tangxifan
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b717903ca1
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[CI] Deploy new test to CI
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2020-12-04 18:51:30 -07:00 |
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tangxifan
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5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
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6001da3a40
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[Arch] Bug fix in tileable I/O arch example
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2020-12-04 17:56:54 -07:00 |
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tangxifan
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73aaa261d8
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[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
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2020-12-04 17:55:25 -07:00 |
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tangxifan
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95c9e19901
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[Tool] Tileable rr_graph now accept I/Os in center grid
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2020-12-04 17:43:35 -07:00 |
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tangxifan
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1d0bdcfeca
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[Arch] Simplify the grid layout modeling
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2020-12-04 17:38:44 -07:00 |
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tangxifan
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7206cafc0e
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[Tool] Minor bug fix
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2020-12-04 17:18:02 -07:00 |
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tangxifan
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1c3f625e41
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[Arch] Force empty tiles at corners for tileable I/O arch example
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2020-12-04 17:11:06 -07:00 |
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tangxifan
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29fd13a42a
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[Tool] Relax restrictions on I/O location in tileable rr_graph builder
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2020-12-04 17:07:01 -07:00 |
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tangxifan
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0cb8457e21
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[Test] Add test case for tileable I/O
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2020-12-04 16:02:47 -07:00 |
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tangxifan
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186eb0f0a4
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[Arch] Add tileable I/O architecture example
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2020-12-04 15:59:39 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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f2e5261d80
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Merge pull request #146 from lnis-uofu/dev
Bug fix in LUT circuit model documentation
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2020-12-04 15:49:05 -07:00 |
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tangxifan
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406edeec89
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[Doc] Typo fix
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2020-12-04 15:07:02 -07:00 |
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tangxifan
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4fe190fa7e
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[Doc] Bug fix in LUT circuit model documentation
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2020-12-04 14:44:27 -07:00 |
ganeshgore
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289d9d2169
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[Bugfix] Honors yosys_tmpl parameter in flow script
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2020-12-03 12:24:24 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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3caf696422
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Merge pull request #144 from lnis-uofu/dev
Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
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2020-12-03 09:57:19 -07:00 |
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tangxifan
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4aa6264b1c
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[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
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tangxifan
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b661c39b04
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[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
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2020-12-02 19:36:36 -07:00 |
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tangxifan
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d71f0537bc
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Merge pull request #143 from lnis-uofu/dev
Critical Bug fix in the XML Syntax when Defining Default Values for A Global Tile Port
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2020-12-02 18:41:25 -07:00 |
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tangxifan
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412fb5bb31
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[Arch] Bug fix due to valid default value parser
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2020-12-02 17:51:50 -07:00 |
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tangxifan
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8350b0f911
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[Doc] Update documentation about default value definition in tile annotation
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2020-12-02 17:08:34 -07:00 |
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tangxifan
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d195b9e32c
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[Tool] Bug fix in XML syntax to define default values for a global tile port
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2020-12-02 17:03:48 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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621f989c9b
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Merge pull request #141 from LNIS-Projects/dev
Add a Test Case to CI which defines global reset port through tile port in VPR architecture
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2020-12-01 08:41:57 -07:00 |
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tangxifan
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290ff028cd
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[Test] Add global_tile_reset test case to CI
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2020-11-30 18:12:47 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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c7604ab94f
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[Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA
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2020-11-30 18:02:00 -07:00 |
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tangxifan
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ff53d2c375
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[HDL] Add new Scan-chain DFF cell
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2020-11-30 17:54:10 -07:00 |
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tangxifan
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ad703ad85b
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[HDL] Add new gpio cell with protection circuitry
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2020-11-30 17:52:39 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
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7a0a3398d4
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[Arch] Add new architecture to test global reset ports defined thru tile ports
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2020-11-30 17:43:41 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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74828ee9ec
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Merge pull request #139 from LNIS-Projects/dev
Update README with latest Github Action badge
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2020-11-30 13:24:19 -07:00 |
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tangxifan
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fc79e83e44
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[Doc] Update README with latest Github Action badge
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2020-11-30 11:57:08 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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8fde74542a
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Merge pull request #135 from LNIS-Projects/dev
Support on Native Fracturable LUT Design
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2020-11-26 13:55:37 -07:00 |
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tangxifan
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cc0114459a
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[Doc] Enrich examples for LUT circuit models
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2020-11-26 13:03:12 -07:00 |
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tangxifan
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62e804215b
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[Doc] Add svg figures for LUT examples
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2020-11-26 12:35:39 -07:00 |
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tangxifan
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dc5e2c99af
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[Test] Add native fracturable LUT4 test to CI
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2020-11-25 23:02:18 -07:00 |
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tangxifan
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3a708cff21
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[Tool] Bug fix to enable nature fracturable LUT design
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2020-11-25 23:01:18 -07:00 |
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tangxifan
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a60bd4d14a
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[Arch] Bug fix in nature fracturable architecture
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2020-11-25 22:48:26 -07:00 |
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ganeshgore
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7db030018c
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[Bug] Fixed variable file location
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2020-11-25 22:44:40 -07:00 |
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tangxifan
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b8559249dc
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[Test] Bug fix in task configuration file
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2020-11-25 22:23:27 -07:00 |
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tangxifan
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26e4db56ad
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[Test] Add new test case for the native fracturable LUT4
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2020-11-25 22:21:23 -07:00 |
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tangxifan
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17070c6405
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[Doc] Update README in openfpga arch directory for native fracturable LUT design
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2020-11-25 22:19:20 -07:00 |
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tangxifan
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f6a667de58
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[Arch] Add openfpga architecture using native fracturable LUT
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2020-11-25 22:18:03 -07:00 |
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tangxifan
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eda671592e
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[Doc] Update README about new keyword about fracturable LUT
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2020-11-25 22:12:56 -07:00 |
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tangxifan
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0f841aa6d1
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[Arch] Add an example architecture using native fracturable LUT
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2020-11-25 22:11:14 -07:00 |
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ganeshgore
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59bd7d0f18
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[Flow] Changed substitute to safe_sustitute option
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2020-11-25 22:09:36 -07:00 |
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ganeshgore
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91d3f289a8
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[Build] Added python setup tools
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2020-11-25 21:11:15 -07:00 |