tangxifan
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c87dbc4880
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start using counter benchmark in regression tests
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2020-06-11 19:31:15 -06:00 |
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tangxifan
|
f73dfa2bcc
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bug fixed in k6_n10_40 architecture
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2020-06-11 19:31:15 -06:00 |
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tangxifan
|
baa2c6b7ef
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update arch to support reset signal for SRAm
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
aac2e8c805
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update openfpga architecture for memory bank usage
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
82b04ae3f0
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add SRAM verilog for memory bank usage
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
3f9afea3e8
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add preconfig testbench test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
288294c23a
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add fast configuration test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
|
73d4c835b7
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add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
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tangxifan
|
a1ec6833c2
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add memory bank example arch xml
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2020-06-11 19:31:13 -06:00 |
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tangxifan
|
2def059b5b
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add standalone configuration protocol to pre config test cases
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2020-06-11 19:31:12 -06:00 |
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tangxifan
|
5f6a790eff
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add new test cases for the standalone memory configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
|
8b5b221a21
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add new architecture for standalone memory organization
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2020-06-11 19:31:12 -06:00 |
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tangxifan
|
a5138113e4
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add fast configuration testcase
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2020-06-11 19:31:12 -06:00 |
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tangxifan
|
8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
|
tangxifan
|
05aa166a9e
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add preconfig testbench cases to regression tests for different configuration protocols
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2020-06-11 19:31:11 -06:00 |
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tangxifan
|
827e2e6713
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file moving in regression tests
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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b5e5182f52
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frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
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2020-06-11 19:31:11 -06:00 |
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tangxifan
|
583c15131b
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change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog
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2020-06-11 19:31:11 -06:00 |
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tangxifan
|
6a72c66eb8
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bug fixed for frame-based configuration memory in top-level full testbench
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2020-06-11 19:31:11 -06:00 |
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tangxifan
|
f5968fda52
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add configurable latch Verilog codes
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2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
1e73fd6def
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create configuration frame example script
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
3fa3b17061
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start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
|
bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
910be3cadb
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massively deploy disable_timing for configure ports in CI
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2020-06-11 19:31:06 -06:00 |
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tangxifan
|
13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
|
fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
1943929353
|
add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
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tangxifan
|
98fbcb5410
|
add time unit test for SDC generation to CI
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
4083fae41a
|
add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
|
2fbf9c2cfc
|
change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
|
2020-06-11 19:31:03 -06:00 |
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tangxifan
|
889bc8dbe8
|
add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
|
889f179ce7
|
add local encoder test case
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2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
f6cea1e17c
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
|
CHARAS SAMY
|
3c781b18d3
|
Added routing benchmark
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2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
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tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
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2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
49edeb119c
|
BugFix : Relative path for refrence benchmark fixed
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
890ead91b9
|
Fixed modelsim include references
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
90f608baea
|
changing task mcnc file for debugging (temporarily now) Will be corrected later
|
2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
417d534121
|
fine tune mcnc example script to run Modelsim simulations easily
|
2020-04-23 16:15:45 -06:00 |
|
tangxifan
|
df85175765
|
fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
|
2020-04-22 21:44:52 -06:00 |
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tangxifan
|
f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
|
2020-04-22 18:24:09 -06:00 |
|
tangxifan
|
726185cd5e
|
add test cases using spypad architecture
|
2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
73e9006372
|
add arch file with spy pads
|
2020-04-22 12:56:09 -06:00 |
|
tangxifan
|
9fb8971281
|
add FPGA arch with spypads to portofilo
|
2020-04-22 11:12:28 -06:00 |
|
tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
|
2020-04-20 13:37:39 -06:00 |