Commit Graph

627 Commits

Author SHA1 Message Date
Victor f7729791e9 add link to file format description file 2024-09-12 12:38:17 +08:00
Victor 6e2e908b83 remove blank lines 2024-09-12 10:18:54 +08:00
Victor ee57aab815 add ident for comment line 2024-09-12 09:50:03 +08:00
Victor 8e97225bc5 add ident 2024-09-12 09:43:57 +08:00
Victor cb9d3d8b03 modify file format 2024-09-11 19:12:47 +08:00
Victor 3d57280afa modify format 2024-09-11 18:31:05 +08:00
Victor 388a8615ee modify file format 2024-09-11 18:23:33 +08:00
Victor 2965026fb2 modify file format 2024-09-11 17:23:37 +08:00
Victor 318ffc6f76 fix issue related to line feed 2024-09-11 16:44:46 +08:00
Victor 989dda9028 modify document format 2024-09-11 14:52:32 +08:00
Victor 6bb54a406d add ident 2024-09-11 13:05:26 +08:00
Victor f9330e13ab fix format issue 2024-09-11 11:09:09 +08:00
victorzh001 04a60ca4b5
Merge branch 'master' into victor_OpenFPGA_dbg 2024-09-10 11:01:47 +08:00
Victor 3ea830e168 Add the reference_file to the index.rst 2024-09-10 10:46:15 +08:00
tangxifan 3b1f51b9d9 [doc] add new options 2024-09-09 13:46:58 -07:00
Victor 8d97ebd980 Add more test cases and update documentation about the YAML file format of this command 2024-09-09 17:49:10 +08:00
Victor 7bacc781d0 update code according to code review comments 2024-09-06 15:39:08 +08:00
tangxifan e7ab7a61f1 [doc] update to use tile name and index when defining clock taps 2024-08-09 18:09:12 -07:00
tangxifan 85c9bdc6f9 [doc] add new format 2024-08-06 17:28:03 -07:00
tangxifan c11a2c7381 [doc] format to resolve latexpdf build errors; now local build passes 2024-08-03 15:03:14 -07:00
chungshien-chai 22d7df5ffb Update doc 2024-07-28 02:40:24 -07:00
chungshien-chai cbe9a46f95 Format and update doc 2024-07-28 00:02:20 -07:00
chungshien-chai 0ff0c3445e Update doc 2024-07-26 13:43:31 -07:00
tangxifan 0c99fcf6f4 [doc] format 2024-07-10 15:07:57 -07:00
tangxifan a390aad0b8 [doc] add new syntax 2024-07-10 15:07:16 -07:00
tangxifan f42884304a [doc] update clock network details 2024-07-09 11:40:41 -07:00
tangxifan bf484dbc70 [doc] add perimeter cb examples on prog clk network 2024-07-08 21:25:12 -07:00
tangxifan 229adebe07 [doc] new option to write_fabric_verilog 2024-07-08 21:06:12 -07:00
tangxifan 8a5c33b1d6 [doc] new option for perimeter cb 2024-07-08 19:01:16 -07:00
tangxifan 4da5150a26 [doc] update for bottom-left tile organization 2024-07-07 14:20:26 -07:00
tangxifan 91f8bb5841 [doc] update figures for ecb 2024-07-07 13:40:01 -07:00
tangxifan e3a258a5ab [doc] typo 2024-07-02 19:31:45 -07:00
tangxifan ec7ca1add1 [doc] add example to example clock network 2024-07-01 21:41:33 -07:00
tangxifan 18e2b994ac [doc] update syntax on clock network file 2024-06-30 22:56:31 -07:00
tangxifan 1094af9f73 [doc] add new options to route clock graph 2024-06-28 12:38:40 -07:00
tangxifan 3fb891094b [doc] add new syntax 2024-06-27 11:02:37 -07:00
tangxifan ec1ad94d4a [doc] add syntax about internal drivers 2024-06-25 13:06:47 -07:00
tangxifan 253e3e0cba [doc] add new syntax for clock network 2024-06-23 17:43:38 -07:00
tangxifan 87a07fb111 [doc] add missing links 2024-06-10 10:57:27 -07:00
tangxifan e6784fdf6c [doc] merge cicd into ci section 2024-06-10 10:47:22 -07:00
tangxifan 3955c80257 [doc] now add tips/notes to readme. Update broken links 2024-06-10 10:42:29 -07:00
tangxifan b491ba03b7 [doc] typo 2024-05-29 10:33:39 -07:00
tangxifan 391b768b3a [doc] syntax 2024-05-21 11:14:12 -07:00
tangxifan 4c6b923b74 [doc] add a figure about ecb 2024-05-21 11:03:58 -07:00
tangxifan 5775187072 [doc] enhance connection block details and restrictions 2024-05-21 10:55:13 -07:00
tangxifan be1d7517c9 [doc] rework out-of-date syntax 2024-05-17 19:25:35 -07:00
tangxifan cb5c8f7c46 [doc] update os and dep info 2024-05-05 16:27:30 -07:00
tangxifan 79c5c0a26a [doc] add more comments 2024-05-02 22:38:39 -07:00
tangxifan f965595d17 [doc] add example file and file format details 2024-05-02 22:37:07 -07:00
tangxifan e4998eebe0 [doc] add new options for write_fabric_hierarchy 2024-05-02 22:29:18 -07:00