tangxifan
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8c1158fc5c
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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tangxifan
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c9d8311a93
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bug fixing for grid-gsb connections in top module when using compact routing
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2019-10-15 18:00:55 -06:00 |
Baudouin Chauviere
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633a12ee08
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Buggy version but need help on debugging
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2019-10-01 14:49:42 -06:00 |
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Baudouin Chauviere
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d5ebe66ad9
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Bug fix
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2019-09-16 10:57:52 -06:00 |
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tangxifan
|
78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
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tangxifan
|
b7f9831bd2
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add statistics for unique GSBs
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2019-07-10 13:08:03 -06:00 |
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tangxifan
|
65f696c1d7
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fix critical bugs in rectangle floorplan
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2019-07-09 17:41:20 -06:00 |
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tangxifan
|
3d8200e217
|
critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
|
d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
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tangxifan
|
3c0ef2067d
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fixed critical bugs in pass_tracks identification and update regression test for tileable arch
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2019-06-25 21:59:38 -06:00 |
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tangxifan
|
4d3b5f12b4
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fixed bugs for UNIVERSAL and WILTON switch blocks
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2019-06-25 14:15:29 -06:00 |
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tangxifan
|
a88263a4c2
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update rr_block writer to include IPINs in XML files
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2019-06-25 11:17:22 -06:00 |
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tangxifan
|
785b560bd5
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sorted drive_rr_nodes for RR GSBs, #. of SBs should be constant now
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2019-06-24 22:46:56 -06:00 |
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tangxifan
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7c38b32eb1
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keep bug fixing for tileable rr_graph generator
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2019-06-21 22:51:11 -06:00 |
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tangxifan
|
baab9c4a21
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basically finished the coding of tileable rr_graph generator. testing to go
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2019-06-20 18:17:07 -06:00 |
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tangxifan
|
0902d1e75a
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c++ string is not working, use char which is stable
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2019-06-13 18:38:46 -06:00 |
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tangxifan
|
8e3ad675e0
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use sstream for rr_block verilog writer
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2019-06-10 16:23:35 -06:00 |
|
tangxifan
|
f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
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tangxifan
|
8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
|
17bc7fc296
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update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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2019-06-08 20:11:22 -06:00 |
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tangxifan
|
8c5ec4572d
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revert string to sprintf
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2019-06-07 20:20:41 -06:00 |
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tangxifan
|
0f1ed19ad0
|
Revert to the use of sprintf instead std::string. Have no idea why string is not working
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2019-06-07 18:54:57 -06:00 |
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tangxifan
|
44ce0e8834
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update gsb unique module detection and fix formal verification port direction
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2019-06-07 17:18:38 -06:00 |
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tangxifan
|
24d53390d8
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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tangxifan
|
472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
|
ce9fc5696c
|
rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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tangxifan
|
8c1e7b799f
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fixed critical bugs in Connection Block Unique Module detection
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2019-06-06 16:31:50 -06:00 |
|
tangxifan
|
873e4d989f
|
fine-tuning Verilog format and node addition to rr_blocks
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2019-06-06 12:48:41 -06:00 |
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tangxifan
|
b9e1b1afc4
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fix a critical bug in num_reserved_sram_ports
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2019-06-05 17:31:01 -06:00 |
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tangxifan
|
0f87ae9886
|
support switch block submodule Verilog generation by segments
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2019-06-05 12:56:05 -06:00 |
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tangxifan
|
c2d8fa00ba
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
|
tangxifan
|
98b82c17be
|
bug fixing for clear RRSwitchBlock
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2019-06-04 14:02:49 -06:00 |
|
tangxifan
|
2c6780ab92
|
add side mirror detection for RRSwitchBlock
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2019-06-04 13:01:22 -06:00 |
|
tangxifan
|
5ed076dfb4
|
fixed a critical bug in rotating
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2019-05-28 17:55:09 -06:00 |
|
tangxifan
|
af91fca1e0
|
add rr_blocks XML writer to help debugging Switch Block Rotation
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2019-05-28 14:52:44 -06:00 |
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tangxifan
|
6f30d3ad05
|
support rotation on segment groups inside RRChan and improve rotatable mirror searching
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2019-05-28 11:25:16 -06:00 |
|
tangxifan
|
0f5666ea11
|
fixed the bug in mirror node direction
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2019-05-27 21:58:21 -06:00 |
|
tangxifan
|
eece161d58
|
keep debugging on Switch Block rotation
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2019-05-27 21:10:30 -06:00 |
|
tangxifan
|
5720217cfd
|
Add copy constructor for RRChan, RRSwitchBlock etc.
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2019-05-27 15:44:34 -06:00 |
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tangxifan
|
1bea9870fc
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developed new rotating methods for RRSwitchBlocks, debugging ongoing
|
2019-05-26 23:35:30 -06:00 |
|
tangxifan
|
4b852afeac
|
skip rotating mirror detection which is too time-consuming
|
2019-05-25 23:41:46 -06:00 |
|
tangxifan
|
22e71f5847
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Add rotate one side of switch block functionality
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2019-05-25 22:48:07 -06:00 |
|
tangxifan
|
858a323228
|
Add more support for rotating Switch Blocks
|
2019-05-25 21:26:35 -06:00 |
|
tangxifan
|
d3eae80e64
|
implemented an native way in finding rotable Switch blocks
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2019-05-25 19:37:18 -06:00 |
|
tangxifan
|
ae0248fbc6
|
debugging SwitchBlock rotating
|
2019-05-24 23:10:30 -06:00 |
|
tangxifan
|
9adc2945c8
|
add rotate functionality for RRSwitchBlock
|
2019-05-24 21:40:16 -06:00 |
|
tangxifan
|
8f4f590ff9
|
update Verilog compact_netlist outputter with RRSwitchBlock classes
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2019-05-23 21:52:12 -06:00 |
|
tangxifan
|
ea8c36ce6e
|
upgrade Verilog SB generator using the RRSwitchBlock
|
2019-05-23 17:37:39 -06:00 |
|
tangxifan
|
4aab93b729
|
update class rr_switch_block and be ready for updating the downstream verilog generator
|
2019-05-22 22:04:31 -06:00 |
|
tangxifan
|
efbc454cdd
|
Add Class for RRSwtichBlock and plug-in to replace the old t_sb
|
2019-05-22 12:34:06 -06:00 |