tangxifan
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233a566774
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Merge pull request #1082 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2023-03-03 16:29:28 -08:00 |
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tangxifan
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b009798ddb
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Merge branch 'xt_clk_arch' of github.com:lnis-uofu/OpenFPGA into xt_clk_arch
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2023-03-03 16:25:32 -08:00 |
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tangxifan
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304925b5ca
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[script] update cmakelist to sync up latest compilation options in VTR
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2023-03-03 16:24:48 -08:00 |
github-actions[bot]
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0bdc9bab12
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Updated Patch Count
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2023-03-04 00:02:33 +00:00 |
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tangxifan
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19e41c6acd
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Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clk_arch
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2023-03-03 15:45:01 -08:00 |
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tangxifan
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d3de6e3bcd
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[lib] update vtr
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2023-03-03 15:31:26 -08:00 |
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tangxifan
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eb5da0ea98
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Merge pull request #1079 from lnis-uofu/dependabot/submodules/yosys-plugins-ab3e14f
Bump yosys-plugins from `ae92491` to `ab3e14f`
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2023-03-03 15:29:08 -08:00 |
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tangxifan
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0d5b9f1be7
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Merge pull request #1080 from lnis-uofu/dependabot/submodules/yosys-9747e55
Bump yosys from `8216b23` to `9747e55`
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2023-03-03 15:28:49 -08:00 |
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tangxifan
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c4ad21451c
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[core] debugging
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2023-03-02 21:54:48 -08:00 |
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tangxifan
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fd1c4039d3
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[test] typo
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2023-03-02 21:37:24 -08:00 |
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tangxifan
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98d8c75d86
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[code] format
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2023-03-02 21:36:08 -08:00 |
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tangxifan
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02b50e3464
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[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
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2023-03-02 21:33:32 -08:00 |
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tangxifan
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b9f7c72a96
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[test] fixed some bugs in arch
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2023-03-02 18:16:59 -08:00 |
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tangxifan
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46510388be
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[core] now fabric generator can wire clock ports to routing blocks
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2023-03-02 12:33:26 -08:00 |
dependabot[bot]
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eb5aa5f5ae
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Bump yosys from `8216b23` to `9747e55`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8216b23` to `9747e55`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8216b23fb7...9747e55d95)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2023-03-02 08:00:16 +00:00 |
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tangxifan
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974263f0fa
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[core] dev
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2023-03-01 23:27:29 -08:00 |
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tangxifan
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099d9f32f4
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[core] dev
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2023-03-01 16:08:15 -08:00 |
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dependabot[bot]
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c39356d302
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Bump yosys-plugins from `ae92491` to `ab3e14f`
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ae92491` to `ab3e14f`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](ae92491a67...ab3e14fbc6)
---
updated-dependencies:
- dependency-name: yosys-plugins
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
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2023-03-01 08:01:24 +00:00 |
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tangxifan
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60ff298987
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[lib] add new feature to enable clock tree connection to global ports of tiles
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2023-02-28 22:36:41 -08:00 |
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tangxifan
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5917446fbe
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[arch] code format
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2023-02-28 22:01:49 -08:00 |
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tangxifan
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780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |
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tangxifan
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9baaf9ea06
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[core] fix compiler warnings
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2023-02-28 20:40:14 -08:00 |
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tangxifan
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7732907623
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[core] format
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2023-02-28 17:01:11 -08:00 |
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tangxifan
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2ff8fb8737
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[core] wrapping up clock routing command
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2023-02-28 16:52:54 -08:00 |
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tangxifan
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bd2608d3e0
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[core] dev
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2023-02-28 15:41:37 -08:00 |
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tangxifan
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6f2572324e
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[core] developing route clock rr_graph command
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2023-02-28 11:52:38 -08:00 |
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tangxifan
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8d5c21b14d
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[core] code format
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2023-02-27 23:00:15 -08:00 |
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tangxifan
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2735b708d3
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[core] reworked the tapping XML syntax
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2023-02-27 22:59:44 -08:00 |
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tangxifan
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ff69664c14
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[core] syntax
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2023-02-27 22:39:12 -08:00 |
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tangxifan
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d4e19edc71
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[core] finishing up clock rr_graph appending
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2023-02-27 22:31:16 -08:00 |
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tangxifan
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9f20d2e639
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[lib] now clock arch supports tap points
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2023-02-27 22:06:13 -08:00 |
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tangxifan
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3a40c5e15f
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[lib] update example of clock arch definition
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2023-02-27 21:49:14 -08:00 |
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tangxifan
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2df1609616
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[core] add a new API to get pin index from a tile
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2023-02-27 21:44:00 -08:00 |
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tangxifan
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0dfe96bcf1
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[core] dev
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2023-02-27 19:37:49 -08:00 |
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tangxifan
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7d0c23c675
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[lib] new api for lowest level clock connections
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2023-02-27 15:16:23 -08:00 |
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tangxifan
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b3dec93eb9
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[core] code format
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2023-02-27 15:12:59 -08:00 |
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tangxifan
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9ec4d690db
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[core] clock edges interconnecting clock tracks across levels
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2023-02-27 15:10:36 -08:00 |
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tangxifan
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b6eace8fac
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[core] now switch id is linked in clock network
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2023-02-27 13:10:54 -08:00 |
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tangxifan
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cae05a14e1
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[core] dev
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2023-02-26 23:10:50 -08:00 |
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tangxifan
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009d711ba5
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[core] code format
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2023-02-26 22:23:41 -08:00 |
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tangxifan
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87a9146082
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[core] adding rr spatial lookup for clock nodes only
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2023-02-26 22:23:17 -08:00 |
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tangxifan
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db36f87dfa
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[core] enhance clock tree arch validation
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2023-02-26 18:39:53 -08:00 |
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tangxifan
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b9e5ae7ae9
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[core] developing
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2023-02-26 18:31:08 -08:00 |
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tangxifan
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780fc0f26d
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[core] developing validators and annotate rr_segment for clock arch
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2023-02-26 18:03:55 -08:00 |
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tangxifan
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4bd952027f
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[core] dev
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2023-02-26 15:31:07 -08:00 |
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tangxifan
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75773ddd4e
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[code] format
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2023-02-26 12:46:29 -08:00 |
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tangxifan
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3db5acfb37
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[core] dev
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2023-02-26 12:40:13 -08:00 |
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tangxifan
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06f77d0435
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[core] dev
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2023-02-25 22:59:07 -08:00 |
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tangxifan
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8f0d94ba73
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[code] format
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2023-02-25 22:43:21 -08:00 |
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tangxifan
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0b33650761
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[core] dev
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2023-02-25 22:41:33 -08:00 |