tangxifan
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3f14fe62c7
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add fast configuration support for configuration chain protocol
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2020-07-15 11:44:23 -06:00 |
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tangxifan
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6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
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9f19c36a89
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use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
ganeshgore
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559564c333
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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0bee70bee6
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finish memory bank configuration protocol support.
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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e14c39e14c
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update Verilog full testbench generation to support memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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8ec8ac4118
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bug fixed in flatten memory organization. Passed verification
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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b9aac3cbdf
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updated fpga verilog testbench generation to support vanilla (standalone) configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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9e176b8d38
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add fast configuration stats to log
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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b5e5182f52
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frame-based configuration protocol is working on k4n4 arch now. Spot bugs in iVerilog about negedge flip-flops
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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bdc9efb38f
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bug fix in top-level testbench for frame-based decoders
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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6a72c66eb8
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bug fixed for frame-based configuration memory in top-level full testbench
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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ece651ade2
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bug fixed in the configuration chian errrors
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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1e2226e1c3
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now use explicit port mapping in the verilog testbenches for reference benchmarks
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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185e574738
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removed redundant include files in all the verilog netlists except the top one
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2020-04-24 20:21:32 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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3369d724e9
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bug fixing in Verilog top-level testbench generation
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2020-04-05 17:50:11 -06:00 |
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tangxifan
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decc1dc4b2
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debugged global gp input/output port support
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2020-04-05 17:39:30 -06:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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77529f4957
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adapt top Verilog testbench generation
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2020-02-26 21:30:21 -07:00 |