Ganesh Gore
|
a6263c44af
|
Updated format
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2023-02-11 18:12:04 -07:00 |
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Ganesh Gore
|
2afb91596f
|
Refactored run_openfpga_task.py
|
2023-02-11 18:04:54 -07:00 |
tangxifan
|
9d8f4c1664
|
[script] format python codes
|
2022-11-21 14:21:31 -08:00 |
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tangxifan
|
9ea4a7c90f
|
[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
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tangxifan
|
55c7b75ab6
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[script] even when power analysis mode is turned off, if users define a act file, still use it
|
2022-08-01 18:13:57 -07:00 |
root
|
0da44ad1fc
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[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
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2022-08-02 08:02:28 +08:00 |
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Ganesh Gore
|
daae02a614
|
Minor documentation update
|
2022-05-08 13:03:16 -06:00 |
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tangxifan
|
74045fc7a1
|
[Script] Fix a bug
|
2022-02-14 23:11:42 -08:00 |
|
tangxifan
|
2990eb7406
|
[Script] Fixed a bug in task run when removing previous runs
|
2022-02-14 22:54:16 -08:00 |
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tangxifan
|
dd40057992
|
[Script] Fixed a bug which causes errors when removing run-directory
|
2022-01-25 13:56:42 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
fc52a4696c
|
Yosys only support added in OpenFPGA
|
2022-01-06 14:44:11 +05:00 |
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Aram Kostanyan
|
a355977420
|
Adding Yosys+Verific support.
|
2021-10-29 18:34:27 +05:00 |
Will
|
c31c1d8b04
|
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
|
2021-08-13 11:08:09 -04:00 |
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tangxifan
|
8baf60603a
|
[Script] Patching the run_fpga_task.py on pin constraint files
|
2021-07-02 15:59:29 -06:00 |
|
Ganesh Gore
|
c67807868c
|
[bugFix] Benchamrk variable declaration
|
2021-07-02 15:26:39 -06:00 |
|
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
Ganesh Gore
|
1de1f2f2e2
|
[FLOW] Variable in capital case
|
2021-07-01 22:26:00 -06:00 |
|
Ganesh Gore
|
81f9dff9ff
|
[Flow] Allows benchmark specific var declaraton
|
2021-07-01 22:19:53 -06:00 |
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tangxifan
|
fd580bb36f
|
[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
|
2021-06-22 11:45:23 -06:00 |
|
tangxifan
|
f9e66e1bae
|
[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
|
2021-06-21 15:27:12 -06:00 |
|
tangxifan
|
fce84e564d
|
[Script] Patch on missing string to show in error message
|
2021-06-18 11:20:35 -06:00 |
|
tangxifan
|
0e01177cf0
|
[Script] Now openfpga flow script output detailed error message when task is not found
|
2021-06-18 11:01:45 -06:00 |
|
tangxifan
|
035043d0d8
|
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
|
2021-03-10 13:36:11 -07:00 |
|
tangxifan
|
5d46537b5b
|
[Script] Allow users to specify custom post-synthesis verilog for simulation
|
2021-03-10 11:45:55 -07:00 |
|
tangxifan
|
aafd87c3f9
|
[Flow] Update flow-run to support custom yosys rewrite scripts
|
2021-03-10 11:36:29 -07:00 |
|
Ganesh Gore
|
67cd9a69b7
|
[Flow] Extended yosys variable subtitution
|
2021-03-08 00:21:07 -07:00 |
Nachiket Kapre
|
2344cdcabc
|
merge
|
2021-02-08 21:11:28 -05:00 |
|
Ganesh Gore
|
df4a397470
|
[Cleanup] Removed deadcode
|
2021-02-03 10:35:14 -07:00 |
|
Ganesh Gore
|
0b82b6439b
|
[Regression] Upgraded runtime enviroment to python3.8
|
2021-01-26 16:40:45 -07:00 |
|
ganeshgore
|
1554f583b7
|
[Flow] Now support explicit variable file for task
|
2020-11-25 17:22:41 -07:00 |
|
ganeshgore
|
45af056304
|
TASK_NAME and TASK_DIR variables are avaialble in config file now
|
2020-07-27 14:14:57 -06:00 |
|
ganeshgore
|
0e46e0d857
|
Updated task.conf format to have transparent shell variables
|
2020-07-27 14:08:58 -06:00 |
|
ganeshgore
|
41585436c8
|
Added external_fabric_key_file key
|
2020-06-12 15:37:12 -06:00 |
|
ganeshgore
|
c1b73efa62
|
Added support for simulation setting file in the task flow
|
2020-06-10 23:12:30 -06:00 |
|
ganeshgore
|
ea4122a8a4
|
Updated openfpga_flow and task file to support sheel run
|
2020-04-06 00:34:36 -06:00 |
|
Ganesh Gore
|
6bb11918dc
|
Updated modelsim and collected result
|
2019-11-16 19:10:04 -07:00 |
|
Ganesh Gore
|
595d2d3070
|
Simple argument shuffle
|
2019-11-01 18:21:26 -06:00 |
|
Ganesh Gore
|
50039a4b6e
|
Added remove run directory option
|
2019-09-21 23:35:56 -06:00 |
|
Ganesh Gore
|
e5c99c8b12
|
Quick terminate on fail added
|
2019-09-13 23:56:38 -06:00 |
|
Ganesh Gore
|
bd9e57bc37
|
Added better task name
|
2019-09-13 23:30:42 -06:00 |
|
Ganesh Gore
|
a6e592247e
|
Replaced options exit_on fail and show_thread logs
|
2019-09-13 22:50:20 -06:00 |
|
Ganesh Gore
|
bcbcd463fe
|
Added pending runs in log
|
2019-09-06 11:48:13 -04:00 |
|
Ganesh Gore
|
48ec1eefcd
|
Added fpga_task cmd options in doc [ci skip]
|
2019-09-02 02:45:05 -06:00 |
|
Ganesh Gore
|
241b001282
|
Added openfpga_task doc
|
2019-09-01 22:15:53 -06:00 |
|
Ganesh Gore
|
ad4c688206
|
Added print for JobID to architecture mapping
|
2019-08-31 22:04:57 -06:00 |
|
Ganesh Gore
|
02137805c7
|
Added python version check in flow and task scripts
|
2019-08-29 22:14:30 -06:00 |
|
Ganesh Gore
|
a25124b58c
|
Added additional PATH variables
|
2019-08-29 21:37:07 -06:00 |