tangxifan
|
2a3950470e
|
remove redudant net source addition in cbs and sbs
|
2020-01-08 19:43:53 -07:00 |
|
tangxifan
|
2306b17d9f
|
added pin duplication support to grid module builder
|
2019-12-25 22:24:44 -07:00 |
|
tangxifan
|
868c573e59
|
remove unused codes and parameters
|
2019-12-24 20:43:29 -07:00 |
|
tangxifan
|
5445047863
|
renamed grid and routing track naming, which are now independent from coordinates
|
2019-12-24 20:17:11 -07:00 |
|
tangxifan
|
0eebdaf942
|
add grid port naming function for modules
|
2019-12-24 15:07:03 -07:00 |
|
tangxifan
|
43e78585ba
|
add routing track naming function for unique modules
|
2019-12-24 14:55:17 -07:00 |
|
tangxifan
|
0dd72999d5
|
deleting legacy codes: fpga_verilog top-level function
|
2019-12-04 15:55:16 -07:00 |
|
tangxifan
|
0daf170e45
|
refactored all the new functions to new source files, ready to delete legacy codes
|
2019-12-04 15:38:42 -07:00 |
|
tangxifan
|
876733f052
|
now we use module manager to generate analysis SDC, being independent from VPR structures
|
2019-11-10 21:15:34 -07:00 |
|
tangxifan
|
a849522be9
|
refactored CB SDC analysis generation
|
2019-11-10 20:15:16 -07:00 |
|
tangxifan
|
8e8e59b0ca
|
give specific name to mux so that we can bind it to SDC generator
|
2019-11-10 19:42:30 -07:00 |
|
tangxifan
|
1f368abfbe
|
refactoring analysis SDC generation
|
2019-11-10 15:40:54 -07:00 |
|
tangxifan
|
bcd8237263
|
refactored grid PnR SDC generator
|
2019-11-09 20:57:54 -07:00 |
|
tangxifan
|
4b5ecc516b
|
refactored SDC SB constrain generation
|
2019-11-09 10:52:15 -07:00 |
|
tangxifan
|
be574b0d45
|
refactored disable routing mux outputs
|
2019-11-08 19:05:05 -07:00 |
|
tangxifan
|
e273c00c9d
|
add refactored disable timing for memory cells
|
2019-11-08 17:38:07 -07:00 |
|
tangxifan
|
33b3705ced
|
refactoring disable outputs sdc generation
|
2019-11-08 11:15:35 -07:00 |
|
tangxifan
|
35e718b32d
|
rename backend sdc generator to be backend assistant
|
2019-11-08 10:20:12 -07:00 |
|
tangxifan
|
14e7744fee
|
start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator
|
2019-11-07 22:20:48 -07:00 |
|
tangxifan
|
56b4ee008e
|
add test for heterogeneous FPGA and fix bugs
|
2019-11-06 17:45:11 -07:00 |
|
tangxifan
|
aac4ccb279
|
fixing bug for heterogeneous FPGAs
|
2019-11-06 11:19:17 -07:00 |
|
tangxifan
|
a308a13d7c
|
use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
|
2019-11-05 15:41:59 -07:00 |
|
tangxifan
|
5d507ae8ee
|
bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
|
2019-11-04 18:05:50 -07:00 |
|
tangxifan
|
3669a47d3b
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
|
tangxifan
|
4398cffaaa
|
single mode is working, multi-mode is under debugging
|
2019-10-29 22:32:36 -06:00 |
|
tangxifan
|
7c116aac2f
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
tangxifan
|
55eea6c4d5
|
rename files to be clear
|
2019-10-27 20:12:48 -06:00 |
|
tangxifan
|
2b06cfc3cf
|
added fabric bitstream generator and fixed critical bugs in top module graph
|
2019-10-27 18:47:33 -06:00 |
|
tangxifan
|
f116351831
|
add instance name for each pb graph node
|
2019-10-26 17:25:45 -06:00 |
|
tangxifan
|
7649d9228e
|
fixed bugs in refactored bitstream generation
|
2019-10-26 16:40:14 -06:00 |
|
tangxifan
|
0a9c89be0b
|
add bitstream writers and start debugging
|
2019-10-26 12:41:23 -06:00 |
|
tangxifan
|
3310bac65b
|
refactored grid bitstream generation
|
2019-10-25 21:49:47 -06:00 |
|
tangxifan
|
4b7a9dfa63
|
add instance name correlation between module and bitstream generation
|
2019-10-25 13:06:48 -06:00 |
|
tangxifan
|
0b687669c8
|
affliate configuration bitstream to sb blocks
|
2019-10-25 10:42:12 -06:00 |
|
tangxifan
|
838173f3c4
|
start refactoring bitstream generator
|
2019-10-24 21:01:11 -06:00 |
|
tangxifan
|
13c62fdcf8
|
add more methods to bitstream manager (renamed from bitstream context)
|
2019-10-24 15:43:29 -06:00 |
|
tangxifan
|
f26dbfe080
|
add instance name for top-level modules to ease readability
|
2019-10-23 20:24:52 -06:00 |
|
tangxifan
|
2787a07f0d
|
start refactoring bitstream generation
|
2019-10-23 17:34:21 -06:00 |
|
tangxifan
|
a18f1305cd
|
add configurable child list to module manager
|
2019-10-23 15:44:13 -06:00 |
|
tangxifan
|
12162a02bc
|
critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
|
tangxifan
|
fb2f003d5b
|
add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
|
tangxifan
|
dafab3907e
|
refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
tangxifan
|
9cf8683acd
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
tangxifan
|
f002f7e30f
|
add const 0 and 1 module Verilog generation
|
2019-10-21 14:17:09 -06:00 |
|
tangxifan
|
b2f57ecf81
|
plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
|
2019-10-21 00:00:30 -06:00 |
|
tangxifan
|
520e145af2
|
move mux_lib to fpga_x2p_setup
|
2019-10-19 19:13:52 -06:00 |
|
tangxifan
|
04f0fbebf7
|
plug in module graph to feed verilog writers
|
2019-10-18 21:59:22 -06:00 |
|
tangxifan
|
7c1bce4b59
|
add module builders for essential gates
|
2019-10-18 20:41:05 -06:00 |
|
tangxifan
|
3b82d62d03
|
start developing module graph builders
|
2019-10-18 20:02:02 -06:00 |
|
tangxifan
|
db38f21412
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |