tangxifan
|
370e3fef83
|
[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
|
2021-10-30 18:03:59 -07:00 |
|
tangxifan
|
7455990ead
|
[Flow] bug fix
|
2021-10-30 16:52:32 -07:00 |
|
tangxifan
|
c8e9dfbeda
|
[Test] bug fix
|
2021-10-30 16:50:57 -07:00 |
|
tangxifan
|
27b82d1473
|
[Flow] bug fix
|
2021-10-30 16:09:31 -07:00 |
|
tangxifan
|
a4cfc84930
|
[Test] Bug fix
|
2021-10-30 16:00:47 -07:00 |
|
tangxifan
|
335347a74f
|
[Test] Bug fix
|
2021-10-30 15:48:25 -07:00 |
|
tangxifan
|
6277234125
|
[Flow] bug fix in BRAM-oriented yosys scripts
|
2021-10-30 15:34:30 -07:00 |
|
tangxifan
|
be47e78289
|
[Arch] Change arch for Sapone test
|
2021-10-30 15:23:19 -07:00 |
|
tangxifan
|
e6cc3c4942
|
[Flow] Enable flatten for dff-related yosys scripts
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2021-10-30 15:12:34 -07:00 |
|
tangxifan
|
ad5cce0ae8
|
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
|
2021-10-30 15:11:07 -07:00 |
|
tangxifan
|
8dea7e80e6
|
[Flow] Update yosys script to not use sdff and dffe
|
2021-10-30 14:56:54 -07:00 |
|
tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
|
tangxifan
|
b7ad61227d
|
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
|
2021-10-30 14:47:37 -07:00 |
|
tangxifan
|
ec184ef532
|
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
|
2021-10-30 14:46:12 -07:00 |
|
tangxifan
|
0b770f3330
|
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
|
2021-10-30 14:36:43 -07:00 |
|
tangxifan
|
59a622a910
|
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
|
2021-10-30 14:34:37 -07:00 |
|
tangxifan
|
978c60e75b
|
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
|
2021-10-30 13:29:38 -07:00 |
|
tangxifan
|
18bab18032
|
[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
|
2021-10-30 13:20:58 -07:00 |
|
tangxifan
|
16de60e943
|
[Test] Turn off ACE2 run in bitstream generation only flows
|
2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
94328351be
|
[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
|
2021-10-30 12:00:06 -07:00 |
|
tangxifan
|
91627abe12
|
[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
|
2021-10-30 11:53:46 -07:00 |
|
tangxifan
|
0a449cc24c
|
[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
|
2021-10-30 11:45:01 -07:00 |
|
tangxifan
|
9c06041ce4
|
[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
|
2021-10-30 11:27:40 -07:00 |
|
tangxifan
|
e8b3c68565
|
[Github] Now use YosysHQ v0.10 release as a submodule
|
2021-10-29 14:19:26 -07:00 |
|
tangxifan
|
104e177e37
|
[Git] Update yosys submodule:
|
2021-10-29 14:17:42 -07:00 |
|
tangxifan
|
aece87b0c8
|
[Github] debugging
|
2021-10-29 14:15:16 -07:00 |
|
tangxifan
|
39fa050b3b
|
[Github] debugging
|
2021-10-29 14:13:02 -07:00 |
|
tangxifan
|
f2ce2e6126
|
[Github] debugging
|
2021-10-29 14:11:45 -07:00 |
|
tangxifan
|
b213faaf81
|
[Git] Add YosysHQ as a submodule in the place of QuickLogic Yosys
|
2021-10-29 13:54:15 -07:00 |
|
tangxifan
|
ddf96fc23a
|
Merge pull request #397 from lnis-uofu/gg_ci_cd_dev
Updated CI documentation
|
2021-10-28 15:27:37 -07:00 |
|
tangxifan
|
2d9ecb5678
|
Merge pull request #400 from lnis-uofu/mult_36
Fixed port names for mult_36x36
|
2021-10-27 09:35:42 -07:00 |
Aram Kostanyan
|
2eef21a1af
|
Fixed port names for mult_36x36
|
2021-10-26 19:14:43 +05:00 |
Ganesh Gore
|
130805d50c
|
Updated CI documentation
|
2021-10-21 15:17:30 -06:00 |
|
tangxifan
|
c35c9bad55
|
Merge pull request #396 from lnis-uofu/gg_ci_cd_dev
[Bugfix] CI docker image build
|
2021-10-20 15:02:43 -07:00 |
ganeshgore
|
c5f00900a9
|
Merge branch 'master' into gg_ci_cd_dev
|
2021-10-20 15:00:13 -06:00 |
|
Ganesh Gore
|
f0d81f7ffc
|
[Bugfix] docker CI build
|
2021-10-20 14:50:17 -06:00 |
|
tangxifan
|
5e912b3c51
|
Merge pull request #392 from lnis-uofu/gg_ci_cd_dev
Make CI Portable
|
2021-10-19 08:33:38 -07:00 |
|
Ganesh Gore
|
de53943208
|
Removed dummy changes
|
2021-10-18 21:43:05 -06:00 |
|
Ganesh Gore
|
ba7a676429
|
Updated docker yml
|
2021-10-18 21:42:39 -06:00 |
|
Ganesh Gore
|
ed5942ce56
|
Added DOCKER_REPO variable
|
2021-10-18 20:00:21 -06:00 |
|
Ganesh Gore
|
32f234f4fc
|
Made LNIS Repo as default
|
2021-10-18 12:54:31 -06:00 |
|
Ganesh Gore
|
fdc9e318fd
|
[CI] Addding conditional docker push
|
2021-10-18 12:18:35 -06:00 |
|
Ganesh Gore
|
d37ae8a8c5
|
Changed docker repo to github repository
|
2021-10-18 11:34:59 -06:00 |
|
Ganesh Gore
|
b47af70bb0
|
Merge branch 'master' into gg_ci_cd_dev
|
2021-10-18 11:17:57 -06:00 |
|
ganeshgore
|
36f847042d
|
Merge pull request #391 from xtofalex/xtof_fixes
Typo fixes, detail error message in case of exception and message formatting in scripts
|
2021-10-18 11:12:07 -06:00 |
Christophe Alexandre
|
c42acec81e
|
Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
|
2021-10-18 10:45:35 +00:00 |
|
Christophe Alexandre
|
c3dd704bf3
|
Fixing typo in run_fpga_flow.py
|
2021-10-18 09:13:42 +00:00 |
|
Christophe Alexandre
|
d411967159
|
Fixing small typo in run_fpga_flow.py
|
2021-10-15 10:01:12 +00:00 |
|
Christophe Alexandre
|
1017a6a619
|
Fixing small typo in openfpga.sh
|
2021-10-11 13:52:31 +00:00 |
|
ganeshgore
|
d85e55aef2
|
Merge pull request #385 from coolbreeze413/add-wget-to-dependencies
add wget to list of dependencies
|
2021-10-07 21:04:29 -06:00 |