BaudouinChauviere
|
361bbc13e3
|
Update func_verify.rst
|
2019-04-01 16:29:42 -06:00 |
|
BaudouinChauviere
|
a176bf3a19
|
Update file_organization.rst
|
2019-04-01 16:28:48 -06:00 |
|
BaudouinChauviere
|
01371ce54d
|
Update customize_subckt.rst
|
2019-04-01 16:27:06 -06:00 |
|
BaudouinChauviere
|
1ea7ec3265
|
Update spice_simulation.rst
|
2019-04-01 16:26:02 -06:00 |
|
BaudouinChauviere
|
cfdc072164
|
Update file_organization.rst
|
2019-04-01 16:25:09 -06:00 |
|
BaudouinChauviere
|
fcc3bf0967
|
Update command_line_usage.rst
|
2019-04-01 16:23:24 -06:00 |
|
BaudouinChauviere
|
f4b72bd4e1
|
Update link_circuit_modules.rst
|
2019-04-01 16:21:59 -06:00 |
|
BaudouinChauviere
|
ce300c196c
|
Update circuit_modules.rst
|
2019-04-01 16:13:23 -06:00 |
|
BaudouinChauviere
|
6e065ef3b3
|
Update tech_lib.rst
|
2019-04-01 16:09:31 -06:00 |
|
BaudouinChauviere
|
aed779ca3d
|
Update spice_sim_setting.rst
|
2019-04-01 16:08:00 -06:00 |
|
BaudouinChauviere
|
4900caaed9
|
Update generality.rst
|
2019-04-01 16:04:17 -06:00 |
|
BaudouinChauviere
|
33df25366c
|
Update eda_flow.rst
Correction fix
|
2019-04-01 16:02:47 -06:00 |
|
BaudouinChauviere
|
d6261f1f59
|
Update motivation.rst
Typo and better explanations correction
|
2019-04-01 15:57:04 -06:00 |
Baudouin Chauviere
|
39f7b0b9a2
|
Update of the doc for better fit with the current version
|
2019-04-01 11:55:28 -06:00 |
|
BaudouinChauviere
|
5dbcfa6d70
|
Repair broken link
|
2019-01-03 18:26:30 +01:00 |
|
BaudouinChauviere
|
28010f6c91
|
Testing another link method
|
2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
30f2ada557
|
Repaired broken links
|
2019-01-03 18:18:03 +01:00 |
|
LNIS-Projects
|
77dd7f3e04
|
correction of the name of the figure
|
2018-12-29 01:45:45 +01:00 |
|
LNIS-Projects
|
0f6ac32f43
|
Further resizing
|
2018-12-29 01:44:24 +01:00 |
|
LNIS-Projects
|
38a3b01520
|
Resize the images
|
2018-12-29 01:42:43 +01:00 |
|
Baudouin Chauviere
|
9ee50de26a
|
Adding information on the layout
|
2018-12-29 01:14:26 +01:00 |
|
Baudouin Chauviere
|
0a5391c14f
|
Addition of some illustrations
|
2018-12-26 18:16:16 +01:00 |
|
LNIS-Projects
|
de7d646fa0
|
Update func_verify.rst
Functional Verification documentation
|
2018-12-26 18:05:24 +01:00 |
|
LNIS-Projects
|
c0626e9a1c
|
Adding the Verification Step from ModelSim
|
2018-12-26 18:00:03 +01:00 |
|
LNIS-Projects
|
c506e16d33
|
Update command_line_usage.rst
Small fix
|
2018-12-22 14:46:15 +01:00 |
|
LNIS-Projects
|
ba303450e2
|
Update file_organization.rst
|
2018-12-22 14:45:00 +01:00 |
|
LNIS-Projects
|
5fa6c84087
|
New fpga_verilog commands documented
|
2018-12-22 14:39:51 +01:00 |
|
LNIS-Projects
|
55459f7906
|
Update index.rst
Reorganization
|
2018-12-10 13:46:38 -07:00 |
|
LNIS-Projects
|
56555fc8a0
|
Update index.rst
Removed abc from the project because included in Yosys
|
2018-12-10 13:46:02 -07:00 |
|
BaudouinChauviere
|
88af64c606
|
Update eda_flow.rst
Distributions compilable added
|
2018-12-05 16:29:07 -07:00 |
|
BaudouinChauviere
|
576feb600f
|
Update eda_flow.rst
Completed with FPGA-Verilog/Bitstream and corrected few errors
|
2018-12-05 16:24:03 -07:00 |
|
BaudouinChauviere
|
0f87fb9c3f
|
Update file_organization.rst
Correction on the routing
|
2018-12-03 14:21:40 -07:00 |
|
BaudouinChauviere
|
e541834bd0
|
Update file_organization.rst
Made similar to the SPICE one
|
2018-12-03 14:20:34 -07:00 |
|
BaudouinChauviere
|
cd301a5bb8
|
Update file_organization.rst
Correction of the hierarchy
|
2018-12-03 14:09:11 -07:00 |
|
BaudouinChauviere
|
9c97125b0d
|
Update spice_simulation.rst
typo
|
2018-12-03 13:42:45 -07:00 |
|
BaudouinChauviere
|
b8f702e16d
|
Update file_organization.rst
Creation of the table for better understanding
|
2018-12-03 13:40:42 -07:00 |
|
BaudouinChauviere
|
10cbd2efef
|
Update index.rst
Commenting the multi mode out until more mature
|
2018-12-03 11:50:13 -07:00 |
|
BaudouinChauviere
|
8e7def7f88
|
Update link_circuit_modules.rst
Correction of typos
|
2018-12-03 11:39:44 -07:00 |
|
BaudouinChauviere
|
f8e801b9d1
|
Merge pull request #1 from LNIS-Projects/Documentation-Update
Update index.rst
|
2018-12-03 11:27:05 -07:00 |
|
BaudouinChauviere
|
a4d29aeb1b
|
Update circuit_model_examples.rst
Typo correction
|
2018-12-03 11:26:04 -07:00 |
|
BaudouinChauviere
|
e39e0219e9
|
Update circuit_modules.rst
Move the examples from this part to their own
|
2018-12-03 10:59:20 -07:00 |
|
BaudouinChauviere
|
7a49ca8ce2
|
Update index.rst
New section in the doc
|
2018-12-03 10:58:50 -07:00 |
|
BaudouinChauviere
|
99769c1510
|
Create circuit_model_examples.rst
Better architecture of the doc
|
2018-12-03 10:58:11 -07:00 |
|
BaudouinChauviere
|
47a214520f
|
Update index.rst
Skip lines
|
2018-12-03 10:32:15 -07:00 |
|
BaudouinChauviere
|
6827549be2
|
Update index.rst
Include the links for the external documentation
|
2018-12-03 10:31:02 -07:00 |
Aurelien Alacchi
|
4a950c6857
|
Flatten_hierarchy_doc
|
2018-10-18 16:28:12 -06:00 |
|
Aurelien Alacchi
|
aa5449c37d
|
Verif_modif_doc_title_2
|
2018-10-17 16:49:55 -06:00 |
|
Aurelien Alacchi
|
6327a4486b
|
Revert "Verif_modif_doc_title"
This reverts commit 8f7f88ebea.
|
2018-10-17 16:47:32 -06:00 |
|
Aurelien Alacchi
|
8f7f88ebea
|
Verif_modif_doc_title
|
2018-10-17 16:45:42 -06:00 |
|
Aurelien Alacchi
|
2cfbe2b997
|
FPGA-Verilog_doc_update
|
2018-10-17 16:38:03 -06:00 |