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OpenFPGA
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6501 Commits

Author SHA1 Message Date
tangxifan 205881d0e7 [core] fixed the bug when using fpga_core instead of fpga_top 2023-06-25 18:03:15 -07:00
tangxifan 2af6d8480d
Merge pull request #1234 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-06-25 17:15:33 -07:00
github-actions[bot] ecf79fcb32 Updated Patch Count 2023-06-26 00:02:40 +00:00
tangxifan 150653287d [core] supporting io naming for verilog testbench generators 2023-06-25 15:29:27 -07:00
tangxifan b72917ecd3
Merge pull request #1232 from lnis-uofu/dependabot/submodules/yosys-f9257d3 
Bump yosys from `8f7a9a0` to `f9257d3`
 2023-06-25 14:39:15 -07:00
tangxifan 987a562e0f [core] fixed the bug when checking mapping status of fpga core ports 2023-06-23 17:21:52 -07:00
tangxifan 523e338d53 [test] debugging 2023-06-23 14:49:52 -07:00
tangxifan 962ba67e36 [test] adding new tests to validate fpga core wrapper naming rules 2023-06-23 14:47:21 -07:00
tangxifan 463332c77a [core] code complete for adding nets between top and core module 2023-06-23 13:21:25 -07:00
tangxifan b30148f8fb [core] apply more sanity checks on top module port 2023-06-23 12:37:46 -07:00
tangxifan 2484150ab6 [core] working on port addition to top module 2023-06-23 12:21:47 -07:00
tangxifan d9f271eaed [lib] fixed a bug where constant string is not initialized 2023-06-23 11:18:36 -07:00
tangxifan 8bd9ae02fd [core] io name map now supports dummy port direction 2023-06-23 11:09:33 -07:00
dependabot[bot] 539e66a1dc
Bump yosys from `8f7a9a0` to `f9257d3` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8f7a9a0` to `f9257d3`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8f7a9a0b66...f9257d3192)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-06-23 06:59:06 +00:00
tangxifan 0811409c4f [lib] support dummy port direction in IoNameMap io 2023-06-22 23:20:22 -07:00
tangxifan 7961223eac [core] enabling io naming rules in fabric builder 2023-06-22 22:18:09 -07:00
tangxifan 4d265c3965 [lib] reworked io name map data structure. Passed I/O test 2023-06-22 17:44:07 -07:00
tangxifan 2f626dc0e8
Merge pull request #1231 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-06-22 17:38:59 -07:00
github-actions[bot] 75cb3166ef Updated Patch Count 2023-06-23 00:02:42 +00:00
tangxifan 4d7bc69c38
Merge pull request #1230 from lnis-uofu/dependabot/submodules/yosys-plugins-7303812 
Bump yosys-plugins from `0ad1af2` to `7303812`
 2023-06-22 12:06:27 -07:00
tangxifan 1981191061
Merge pull request #1229 from lnis-uofu/dependabot/submodules/yosys-8f7a9a0 
Bump yosys from `104edb4` to `8f7a9a0`
 2023-06-22 12:06:08 -07:00
dependabot[bot] 615934b2d6
Bump yosys-plugins from `0ad1af2` to `7303812` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `0ad1af2` to `7303812`.
- [Commits](0ad1af26a2...73038124b0)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-06-22 06:59:40 +00:00
dependabot[bot] 05d2caf6b8
Bump yosys from `104edb4` to `8f7a9a0` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `104edb4` to `8f7a9a0`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](104edb4587...8f7a9a0b66)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-06-22 06:59:35 +00:00
tangxifan a628a1e7b0 [lib] add missing file 2023-06-21 23:02:43 -07:00
tangxifan b8d89d2a5c [lib] code format 2023-06-21 22:51:38 -07:00
tangxifan 227d147dca [lib] add an example file 2023-06-21 22:51:15 -07:00
tangxifan 77b082ab55 [src] debugging 2023-06-21 22:50:37 -07:00
tangxifan f3c07d6138 [lib] finish the io for io naming rules 2023-06-21 21:48:52 -07:00
tangxifan 2ed86d1897 [lib] developing io for io naming rule 2023-06-21 18:08:45 -07:00
tangxifan b42677aa9d [lib] developing the io name mapping data structure 2023-06-21 17:33:40 -07:00
tangxifan 7c11e755fb
Merge pull request #1228 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-06-21 17:11:53 -07:00
github-actions[bot] 0e033de9b5 Updated Patch Count 2023-06-22 00:02:36 +00:00
tangxifan 61544af2b4 [core] start adding new options 2023-06-21 14:01:00 -07:00
tangxifan 2e7d78896c
Merge pull request #1227 from lnis-uofu/dependabot/submodules/yosys-104edb4 
Bump yosys from `2595471` to `104edb4`
 2023-06-21 11:07:56 -07:00
dependabot[bot] 462fbdd52d
Bump yosys from `2595471` to `104edb4` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `2595471` to `104edb4`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](25954715f0...104edb4587)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-06-21 06:59:24 +00:00
tangxifan 8d62ac1ec0
Merge pull request #1226 from lnis-uofu/xt_adder 
Enable Adder mapping and validation on FPGA architecture using hard adders
 2023-06-20 18:25:25 -07:00
tangxifan 84edd41342 [test] fixed the bug in adder mapping 2023-06-20 17:09:31 -07:00
tangxifan dba48fb171 [test] reworking adder mapping flow to validate carry chain mapping 2023-06-20 16:57:08 -07:00
tangxifan ce71f097b4
Merge pull request #1224 from lnis-uofu/dependabot/submodules/yosys-2595471 
Bump yosys from `8b2a001` to `2595471`
 2023-06-20 14:22:37 -07:00
dependabot[bot] 781c0c6f71
Bump yosys from `8b2a001` to `2595471` 
Bumps [yosys](https://github.com/YosysHQ/yosys) from `8b2a001` to `2595471`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](8b2a001021...25954715f0)

---
updated-dependencies:
- dependency-name: yosys
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-06-20 06:59:10 +00:00
tangxifan eda0baac28
Merge pull request #1222 from lnis-uofu/xt_fpga_core 
Support ``fpga_core`` wrapper insertion
 2023-06-19 20:12:58 -07:00
tangxifan fd8f371d85 [test] add missing file 2023-06-19 16:44:11 -07:00
tangxifan b2d1d1b6bd [core] fixed a bug on fpga bitstream when supporting fpga_core 2023-06-19 14:40:38 -07:00
tangxifan 299b42873d [core] fix no warning build 2023-06-19 13:01:43 -07:00
tangxifan efc9bf9907 [test] added new test case to validate bitstream generation 2023-06-19 12:40:37 -07:00
tangxifan a4f26798b0 [core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc 2023-06-19 11:59:48 -07:00
tangxifan 63ee0c980e [core] fixed some bugs 2023-06-18 22:12:54 -07:00
tangxifan d9499f2b40 [core] now fpga bitstream supports the wrapper module 2023-06-18 21:58:36 -07:00
tangxifan bdda695cc0 [core] format 2023-06-18 21:18:35 -07:00
tangxifan cef573529d [core] now fpga verilog can output fpga core netlist 2023-06-18 21:17:50 -07:00