tangxifan
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2b4beb632c
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[doc] fix a bug in including io information file format
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2022-07-26 15:50:35 -07:00 |
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tangxifan
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bf2b1da801
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[doc] add the new command file format to documentation
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2022-07-26 14:06:07 -07:00 |
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tangxifan
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907308ee0f
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[Doc] Update bitstream distribution file format
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2022-03-29 20:09:24 +08:00 |
taoli4rs
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781250f0bb
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Fix a small typo to trigger the CI flow.
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2022-03-22 16:36:45 -07:00 |
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tangxifan
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6ff69d26b9
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[Doc] An example to the documentation about the new feature in tile_annotation
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2022-03-20 13:12:13 +08:00 |
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tangxifan
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123bb70cb3
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[Doc] More explanantion on the use of config_enable attribute for circuit ports
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2022-02-23 15:53:58 -08:00 |
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tangxifan
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b78e58d9bf
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[Doc] Update doc about big endian syntax in bus group file format
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2022-02-18 23:07:18 -08:00 |
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tangxifan
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8116141210
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[Doc] Update documentation on the bus group feature
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2022-02-18 15:46:25 -08:00 |
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tangxifan
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37d8617a5c
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[Doc] Update due to new options
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2022-02-17 19:45:37 -08:00 |
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tangxifan
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4a78bcf5d3
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[Doc] update file format about bus group
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2022-02-17 15:15:05 -08:00 |
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tangxifan
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796428d848
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[Doc] Add documentation about bus group file format
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2022-02-17 14:22:21 -08:00 |
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tangxifan
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2b5fded2a9
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[Doc] Update documentation on the new option
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2022-02-01 13:25:58 -08:00 |
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tangxifan
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b7b0a2a5d8
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[Doc] Update doc about the new option
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2022-02-01 12:19:26 -08:00 |
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tangxifan
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63f44adf15
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[FPGA-Verilog] Now have a new option ``--use_relative_path``
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2022-01-31 12:48:05 -08:00 |
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tangxifan
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a9a56686e2
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[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
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2022-01-26 11:10:29 -08:00 |
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tangxifan
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25143d07f1
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[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
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2022-01-25 13:37:54 -08:00 |
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tangxifan
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a4659020f2
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Merge branch 'master' into time_stamp
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2022-01-25 12:11:35 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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bd158311c5
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Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
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2022-01-18 14:07:41 +05:00 |
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Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
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Aram Kostanyan
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fb2e4377c8
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Added missing changes from previous commit.
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2022-01-17 19:42:40 +05:00 |
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Aram Kostanyan
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2b008177e7
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Updated documentation.
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2022-01-17 14:58:20 +05:00 |
Awais Abbas
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54d4f30592
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OpenFPGA Documentation updated for yosys only support
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2022-01-14 16:14:48 +05:00 |
nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
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Aram Kostanyan
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a355977420
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Adding Yosys+Verific support.
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2021-10-29 18:34:27 +05:00 |
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tangxifan
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57159fc121
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[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
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2021-10-10 17:46:45 -07:00 |
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tangxifan
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40b589dc6d
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[Doc] Update documentation about the clock definition for programming clocks in simulation settings
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2021-10-06 13:50:33 -07:00 |
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tangxifan
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03bcf6dee5
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[Doc] Update documenation for the new option ``--keep_dont_care_bits``
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2021-10-05 19:23:42 -07:00 |
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tangxifan
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ff339312f6
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[Doc] Update documentation about the limitations of multi-region configuration protocols
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2021-10-05 11:55:10 -07:00 |
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tangxifan
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9a7e0f761a
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[Doc] Add fabric bitstream file format for QL memory bank
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2021-10-04 12:29:49 -07:00 |
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tangxifan
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a01fa7c282
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[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
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2021-10-04 12:09:42 -07:00 |
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tangxifan
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b0a97a7052
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[Doc] Update doc about WLR usage for QL memory bank
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2021-09-27 10:24:04 -07:00 |
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tangxifan
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f9bceff33a
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[Doc] Update documentation for the flatten BL/WL protocols
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2021-09-25 20:44:45 -07:00 |
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tangxifan
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10774dc15c
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[Doc] Updated documentation about new syntax in fabric key
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2021-09-21 17:01:52 -07:00 |
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tangxifan
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d9d959709c
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[Doc] Add missing figures
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2021-09-20 20:31:53 -07:00 |
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tangxifan
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3146d2484f
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[Doc] Update documentation on the WLR definition for circuit model
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2021-09-20 17:21:33 -07:00 |
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tangxifan
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73d21c9730
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[Doc] Update doc about how to use the QuickLogic memory bank
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2021-09-10 15:30:37 -07:00 |
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tangxifan
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43afaca17c
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[Doc] Add more details about the new syntax
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2021-07-01 23:51:54 -06:00 |
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tangxifan
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0851075bc9
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[Doc] Update documentation about the new feature in pin constraint file
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2021-07-01 23:47:36 -06:00 |
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tangxifan
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ac9046b7d2
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[Doc] Remove ``define_simulation.v`` since it is no longer needed.
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2021-06-29 15:38:35 -06:00 |
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tangxifan
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30027b8c15
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[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
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2021-06-25 15:27:15 -06:00 |
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tangxifan
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11d0283771
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[Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream'
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2021-06-25 15:11:12 -06:00 |
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tangxifan
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507f5ee54c
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[Doc] Update documentation about time unit support in writing simulation file
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2021-06-25 10:34:43 -06:00 |
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tangxifan
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8e2ba718d0
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[Doc] update documentation on the new option '--testbench_type'
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2021-06-25 10:16:48 -06:00 |
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tangxifan
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779437cd37
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[Doc] Update documentation to remove out-of-date options related to signal_init
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2021-06-24 17:07:15 -06:00 |
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tangxifan
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9585e1d3b5
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[Doc] Update documentation about 'default_net_type' option in testbench generators
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2021-06-14 14:00:34 -06:00 |
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tangxifan
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b719419931
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[Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command
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2021-06-09 16:59:02 -06:00 |
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tangxifan
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54a53bc988
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[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol
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2021-06-07 17:58:00 -06:00 |
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tangxifan
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0fee741008
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[Doc] Update documentation on the minor changes on fabric bitstream file format
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2021-06-07 14:22:35 -06:00 |