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1076 Commits

Author SHA1 Message Date
tangxifan 2ce2fb269a [HDL] Added a different FF model which is designed to drive WLW only 2021-09-28 12:35:13 -07:00
tangxifan 6469ee3048 [HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs 2021-09-28 12:21:54 -07:00
tangxifan 1ca1b0f3e9 [Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests 2021-09-22 15:58:05 -07:00
tangxifan 655b195d8b [Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level 2021-09-22 15:56:44 -07:00
tangxifan a98df811ed [Arch] Bug fix: wrong circuit model name was used for CCFF 2021-09-22 15:50:47 -07:00
tangxifan 53da5d49fe [Arch] Correct XML syntax errors 2021-09-22 15:48:14 -07:00
tangxifan 3cfd5c3531 [Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks 2021-09-22 15:04:59 -07:00
tangxifan 212c5bd642 [Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization 2021-09-22 15:04:19 -07:00
tangxifan b0aaab9c03 [Test] Bug fix due to mismatches in device layout between fabric key and VPR settings 2021-09-22 11:32:13 -07:00
tangxifan efed268585 [Test] Deploy new test (for multi-region QL memory bank) to basic regression tests 2021-09-22 11:30:08 -07:00
tangxifan abfa380333 [Test] Added a test case to validate the fabric key of 2-region QL memory bank 2021-09-22 11:27:09 -07:00
tangxifan 337ed33b68 [Test] Added a sample fabric key for 2-region QL memory bank 2021-09-22 11:25:16 -07:00
tangxifan 7db7e2d8f6 [Test] Deploy the new test case for multi region QL memory bank to basic regression tests 2021-09-22 10:05:27 -07:00
tangxifan d0fe12fadd [Arch] Add an example OpenFPGA architecture for 2-region QL memory bank 2021-09-22 10:03:39 -07:00
tangxifan 51fc222d61 [Test] Added a new test case for multi-region QL memory bank 2021-09-22 10:01:33 -07:00
tangxifan ab42239b94 [Test] Bug fix in the fabric key 2021-09-21 16:44:58 -07:00
tangxifan f57aceff87 [Test] Deploy the load external key test case for ql memory bank to basic regression tests 2021-09-21 16:25:14 -07:00
tangxifan aad47ffbc6 [Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric 2021-09-21 16:22:50 -07:00
tangxifan 1412121541 [Test] Added a new test to validate the fabric key parser for QL memory bank 2021-09-21 16:20:24 -07:00
tangxifan cd0d8b86fa [Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank 2021-09-21 15:55:34 -07:00
tangxifan 7327850cf3 [Test] Deploy the fabric key test case for ql memory bank to basic regression tests 2021-09-21 15:43:54 -07:00
tangxifan dc2d1d1c3c [Test] Add a new test case to validate the correctness of fabric key file for ql memory bank 2021-09-21 15:42:20 -07:00
tangxifan d36d1ebee2 [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tangxifan 0450d57d82 [Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR 2021-09-20 16:05:01 -07:00
tangxifan 3f6ac41868 [Test] Deploy the WLR test to the basic regression tests 2021-09-20 11:21:58 -07:00
tangxifan 60fc3ab36c [Test] Added a new test case for the WLR memory bank 2021-09-20 11:20:36 -07:00
tangxifan 5c1c428ea5 [HDL] Updated cell library with the SRAM cell with Read Enable signal 2021-09-20 11:13:36 -07:00
tangxifan cd2978a434 [Arch] Added a new architecture example which shows how to use the memory bank with readback functionality 2021-09-20 11:13:02 -07:00
tangxifan 81a2ad58df [Test] Deploy the ql memory bank test case to basic regression tests (run on CI) 2021-09-09 13:48:30 -07:00
tangxifan b82cfdf555 [Test] Add the QL memory bank test to regression test cases 2021-09-09 09:29:21 -07:00
tangxifan 6be3c64f1c [Arch] Add an example architecture using the physical design friendly memory bank organization 2021-09-09 09:22:27 -07:00
tangxifan 6adf439081 Merge remote-tracking branch 'upstream/master' 2021-09-01 14:19:00 -07:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00