tangxifan
|
23f43459bd
|
Merge pull request #1773 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-02 21:23:35 -07:00 |
github-actions[bot]
|
94c6b6322a
|
Updated Patch Count
|
2024-08-03 04:00:29 +00:00 |
tangxifan
|
0edd5529c3
|
Merge pull request #1772 from lnis-uofu/xt_fkey
[core] fixed a bug where pb pin fixup does not support perimeter cb
|
2024-08-02 21:00:06 -07:00 |
tangxifan
|
8a07564d80
|
Merge branch 'master' into xt_fkey
|
2024-08-02 19:11:49 -07:00 |
tangxifan
|
57adf97fd4
|
[test] fixed some bugs in clock arch
|
2024-08-02 18:34:59 -07:00 |
tangxifan
|
2e6b311d04
|
[core] add more details to debug messages
|
2024-08-02 18:33:43 -07:00 |
tangxifan
|
91c4336a4a
|
[test] add a new testcase to validate 3-layer clock architecture
|
2024-08-02 18:18:49 -07:00 |
tangxifan
|
eeaa3373c6
|
[core] code format
|
2024-08-02 17:48:47 -07:00 |
tangxifan
|
82cf7bbb8c
|
[core] Add verbose mode on find_node() for clock rr graph
|
2024-08-02 17:47:41 -07:00 |
tangxifan
|
84c2b27c7b
|
[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
|
2024-08-02 17:24:44 -07:00 |
tangxifan
|
ae1100ceba
|
[core] cleanup debug message
|
2024-08-02 17:05:59 -07:00 |
tangxifan
|
1ec5847d5a
|
[core] typo
|
2024-08-02 14:27:43 -07:00 |
tangxifan
|
f44c45bdd3
|
[core] code format
|
2024-08-02 14:23:35 -07:00 |
tangxifan
|
6a7929973d
|
Merge pull request #1771 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-08-02 14:21:55 -07:00 |
github-actions[bot]
|
2986a5c5ee
|
Updated Patch Count
|
2024-08-02 21:21:28 +00:00 |
tangxifan
|
f7e30b9974
|
[core] fixed a bug where pb pin fixup does not support perimeter cb
|
2024-08-02 14:21:22 -07:00 |
tangxifan
|
39f6cd13d9
|
Merge pull request #1770 from lnis-uofu/xt_fkey
[lib] now fabric key assistant can cross-check mismatches between reference and input fabric keys
|
2024-08-02 14:21:08 -07:00 |
tangxifan
|
ad38b52a23
|
[lib] code format
|
2024-08-02 12:41:00 -07:00 |
tangxifan
|
1a13c5f815
|
[lib] now fabric key assistant can cross-check mismatches between reference and input fabric keys
|
2024-08-02 12:31:55 -07:00 |
tangxifan
|
d7a83ecbec
|
Merge pull request #1768 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-31 14:06:12 -07:00 |
github-actions[bot]
|
c05b06ef61
|
Updated Patch Count
|
2024-07-31 21:05:29 +00:00 |
tangxifan
|
6ea1feb445
|
Merge pull request #1756 from chungshien/openfpga-overwrite-bits
Openfpga support setting bitstream bit manually
|
2024-07-31 14:05:04 -07:00 |
chungshien
|
b3c8c529d5
|
Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
|
2024-07-31 12:25:37 -07:00 |
chungshien-chai
|
766df0a1b5
|
Improve Port Parser
|
2024-07-31 12:19:30 -07:00 |
tangxifan
|
4defb9e514
|
Merge pull request #1766 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-30 21:00:01 -07:00 |
github-actions[bot]
|
c88774bf5e
|
Updated Patch Count
|
2024-07-31 03:59:21 +00:00 |
tangxifan
|
6a88e7befb
|
Merge pull request #1765 from lnis-uofu/xt_clkntwk2
Multiple Enhancements on Clock Network v2.0
|
2024-07-30 20:59:02 -07:00 |
tangxifan
|
d6db51f29e
|
[core] code format
|
2024-07-30 19:09:31 -07:00 |
tangxifan
|
ef6b6f8e40
|
[core] remove warnings
|
2024-07-30 18:50:49 -07:00 |
tangxifan
|
ae95357991
|
[core] code format
|
2024-07-30 15:40:41 -07:00 |
tangxifan
|
a2c3af60d7
|
[core] fixed a bug where unique cb module is not considered as entry point
|
2024-07-30 15:39:44 -07:00 |
tangxifan
|
3181f2d5a3
|
[test] add a new test to validate multiple entry points for a clock network
|
2024-07-30 14:17:14 -07:00 |
tangxifan
|
687f03fd77
|
[test] add a new test to validate clock network on module named by index
|
2024-07-30 14:06:53 -07:00 |
tangxifan
|
853883cd36
|
[core] code format
|
2024-07-30 12:56:03 -07:00 |
tangxifan
|
f9f9aab7d9
|
[test] typo
|
2024-07-30 12:50:14 -07:00 |
tangxifan
|
ad275fba44
|
[test] add a new test to validate clock network entry point on a y-direction cb
|
2024-07-30 12:48:35 -07:00 |
tangxifan
|
b6b038a73d
|
[test] add a new arch to test y- entry point of clock network
|
2024-07-30 12:40:41 -07:00 |
tangxifan
|
234eee19ae
|
[core] revert
|
2024-07-30 12:29:32 -07:00 |
tangxifan
|
6a5e0e2f49
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into xt_clkntwk2
|
2024-07-30 12:23:31 -07:00 |
tangxifan
|
0aa9c4c6af
|
Merge pull request #1764 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-07-30 11:42:29 -07:00 |
github-actions[bot]
|
a2906c4c94
|
Updated Patch Count
|
2024-07-30 18:42:13 +00:00 |
tangxifan
|
9ef31e6aec
|
Merge pull request #1762 from lnis-uofu/dependabot/submodules/yosys-c788484
Bump yosys from `960bca0` to `c788484`
|
2024-07-30 11:41:55 -07:00 |
tangxifan
|
44f63cb897
|
Merge pull request #1763 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-9eef18c
Bump vtr-verilog-to-routing from `ddc3ac4` to `9eef18c`
|
2024-07-30 11:41:42 -07:00 |
dependabot[bot]
|
4d479f9d8c
|
Bump vtr-verilog-to-routing from `ddc3ac4` to `9eef18c`
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `ddc3ac4` to `9eef18c`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](ddc3ac408a...9eef18c4fa )
---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-30 07:00:11 +00:00 |
dependabot[bot]
|
9e59a1fa4a
|
Bump yosys from `960bca0` to `c788484`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `960bca0` to `c788484`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](960bca0196...c788484679 )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-30 07:00:09 +00:00 |
chungshien-chai
|
ca48841ae3
|
Pass in the OpenFPGA root dir
|
2024-07-29 11:04:03 -07:00 |
tangxifan
|
5f45d13bfd
|
Merge branch 'master' into openfpga-overwrite-bits
|
2024-07-29 16:22:02 +08:00 |
tangxifan
|
7f9dffec89
|
Merge pull request #1760 from lnis-uofu/dependabot/submodules/yosys-960bca0
Bump yosys from `610d27d` to `960bca0`
|
2024-07-29 16:06:55 +08:00 |
dependabot[bot]
|
3c547f2131
|
Bump yosys from `610d27d` to `960bca0`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `610d27d` to `960bca0`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](610d27dc1c...960bca0196 )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-29 06:09:43 +00:00 |
chungshien-chai
|
3e3f089823
|
Get the filepath using definition under [OpenFPGA_SHELL]
|
2024-07-28 19:24:48 -07:00 |