20ba0e1dd5
[test] add new testcases to validate options of write_fabric_pin_physical_location
2024-04-11 15:06:50 -07:00
0c680ec426
[test] now test regex as module name for fabric pin physical location
2024-04-11 15:01:19 -07:00
4dedee4011
[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
2024-04-11 12:59:13 -07:00
c63cee458b
[script] adapt code format for python
2024-04-10 12:58:05 -07:00
3824b006cc
[test] add new golden outputs
2024-03-29 12:06:00 -07:00
f0639b4567
[test] add new testcase to basic reg test
2024-03-29 11:56:11 -07:00
20386945bd
[test] add a new testcase to validate dump waveform
2024-03-29 11:53:55 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
2bd60dad11
[script] now timing extraction focus on the last found results
2023-12-12 14:10:13 -08:00
592e2e310c
[script] typo
2023-12-12 13:45:23 -08:00
b182b47d0b
[test] use a timing-focus tool path for a testcase
2023-12-12 13:28:35 -08:00
c5cc05a9f5
[script] add a new example default tool path config with a focus on timing
2023-12-12 13:22:50 -08:00
f689ef7654
[script] format
2023-12-12 13:15:03 -08:00
4c0f6e2273
[script] syntax
2023-12-12 13:14:47 -08:00
e753e6d22c
[script] syntax
2023-12-12 13:13:51 -08:00
d9db78ac30
[script] now run fpga task has a new option ``default_tool_path``
2023-12-12 13:11:48 -08:00
1a4aaaf759
[script] update openfpga flow to support args for default tool path
2023-12-12 10:00:50 -08:00
a7b22163a8
[script] fixe the mismatch on keywords against latest vpr
2023-12-12 09:52:42 -08:00
5c839c1858
[test] debug
2023-12-08 13:52:52 -08:00
6a5df804b9
[test] add new testcase to reg test
2023-12-08 13:46:54 -08:00
99f1c5493c
[test] add a new testcase to support vcs
2023-12-08 13:45:23 -08:00
a1169beaf0
Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:34:49 -08:00
7475a002b6
Update repack_design_constraints.xml by changing the separater between pb type and pin name
...
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
2023-12-04 13:33:55 -08:00
6055a42196
add test case
2023-12-01 03:04:32 -08:00
dff03e7993
[test] enable missing options in the arch used by benchmark sweeping tests
2023-11-14 09:45:02 -08:00
0b473e3454
[test] fixed the bug in single-mode lut testcase
2023-11-14 09:35:26 -08:00
d108284105
[test] update arch to keep golden outputs
2023-11-14 09:31:07 -08:00
913434b70d
[test] fixed the bug that golden netlists are modified
2023-11-14 09:28:57 -08:00
59d086a27f
[test] try to keep the golden inputs
2023-11-14 09:25:45 -08:00
1b8748abb4
[core] update vtr
2023-11-13 14:21:34 -08:00
d78f18d235
[test] add new testcase
2023-11-13 14:11:34 -08:00
8e875f3453
[test] add a new test case to validate the new feature
2023-11-02 21:08:36 -07:00
c6f33bcd7f
[test] add new tests to cover the new features
2023-10-06 18:41:57 -07:00
7d83fc914c
[core] ad a new test case
2023-10-06 18:31:54 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
60b8c396dc
[test] add a new test
2023-09-25 21:25:21 -07:00
a4f53c64c6
[test] fixed a bug
2023-09-25 19:28:19 -07:00
663c9c9fa1
[test] add a new test to validate the tile port merge feature
2023-09-25 18:34:34 -07:00
a1ed277a88
[test] typo
2023-09-23 15:12:02 -07:00
00e1a5df11
[test] fixed some bugs
2023-09-23 12:44:47 -07:00
195aa7a9a8
[test] developing new test to increase coverage on module renaming
2023-09-23 12:40:20 -07:00
f3279bd885
[test] now use 4x4 fabric to check the using index netlists
2023-09-20 22:49:47 -07:00
eeb1bd6662
[core] fixed some bugs
2023-09-17 23:16:15 -07:00
3fd60a165d
[test] typo
2023-09-17 17:42:15 -07:00
11e976ec92
[test] add a new test to validate renaming on fpga top/core modules
2023-09-17 17:38:37 -07:00
0ef1e0bde5
[test] add a new test to validate renaming rules
2023-09-17 13:29:12 -07:00
559fa45d89
[test] add a new test to validate module renaming using index
2023-09-16 17:55:52 -07:00
1287097ce5
[test] update golden netlists
2023-09-06 22:51:38 -07:00
401f8098a6
[test] update golden copies
2023-09-06 17:35:03 -07:00
db0bb291c2
[test] update settings
2023-08-22 15:22:48 -07:00
tangxifan
chungshien
Yitian4Debug
ubuntu