tangxifan
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19472ace4e
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renaming files
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2019-08-20 21:01:38 -06:00 |
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tangxifan
|
29104b6fa5
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rework on the circuit model ports and start prototyping mux Verilog generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
69039aa742
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developed subgraph extraction and start refactoring mux generation
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
bee070d7cc
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start plug in MUX library
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2019-08-20 15:24:53 -06:00 |
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tangxifan
|
b66e120366
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patch on local encoders for unused configuration, avoid chip-burn issues
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2019-08-16 15:32:23 -06:00 |
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tangxifan
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4eb046760b
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still fixing the bug for local encoders, spot one in the special basis, ongoing bugfix
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2019-08-15 21:57:59 -06:00 |
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tangxifan
|
f57495feba
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Now we can also auto-generate the Verilog for a mux2 std cell
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2019-08-06 15:19:01 -06:00 |
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tangxifan
|
afa468a442
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hotfix in minor Verilog generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
|
b4f3dfc82d
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bug fixing for local encoder's bitstream generation
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2019-08-06 14:17:57 -06:00 |
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tangxifan
|
3a490fdd59
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bug fixing on the port map alignment
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
890ff05628
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bug fixing and get ready for testing
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
c08c136844
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set a working range for the encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
386bddacd1
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updated bitstream generator for local encoders
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
557b1af633
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add Verilog generation for local encoders, bitstream upgrade TODO
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2019-08-06 14:17:56 -06:00 |
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tangxifan
|
003883b13b
|
implementing the local encoders
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
fb2ca66ce9
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start adding submodules of local encoders to multiplexer
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2019-08-06 14:17:55 -06:00 |
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tangxifan
|
8b8e18a8de
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bug fixing for mux subckt names
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2019-07-17 08:59:57 -06:00 |
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tangxifan
|
a2505ff16a
|
turn on std cell explicit port map
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2019-07-17 08:36:09 -06:00 |
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tangxifan
|
dcc96bf7f5
|
bug fixing
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2019-07-17 08:25:52 -06:00 |
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tangxifan
|
6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
Baudouin Chauviere
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69014704ef
|
Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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Baudouin Chauviere
|
25f5bc7792
|
Latest version, not stable yet but close
|
2019-07-09 08:34:01 -06:00 |
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Baudouin Chauviere
|
8f5ad2eb67
|
Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
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Baudouin Chauviere
|
f189ef1d8f
|
Done with the submodules
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2019-07-01 14:24:09 -06:00 |
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Baudouin Chauviere
|
370ce23646
|
Mux explicit verilog done
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2019-07-01 13:58:24 -06:00 |
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Baudouin Chauviere
|
863e8677c0
|
Further add new functions to tree
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2019-07-01 12:12:36 -06:00 |
AurelienUoU
|
ec504049ef
|
Update Testbenches to increase accuracy + commented compact routing option until debug
|
2019-06-26 10:01:12 -06:00 |
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tangxifan
|
1776ae3ec8
|
add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
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tangxifan
|
f43955037c
|
remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
giacomin
|
ceee28226e
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
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giacomin
|
8b520349e7
|
fixed a bug for rram based fpga when using explicit verilog port mapping
|
2019-05-20 16:44:47 -06:00 |
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AurelienUoU
|
99beeb48cc
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 16:42:27 -06:00 |
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AurelienUoU
|
a3656dde45
|
Add missing Verilog source, Archictecture folder and Testbenches correction
|
2019-05-13 16:41:35 -06:00 |
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Baudouin Chauviere
|
2019840d7c
|
cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |