tangxifan
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f5b6774eb0
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[core] add code comments and fixed some bugs
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2024-06-28 12:21:33 -07:00 |
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tangxifan
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53ba2f0c29
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[core] fixed a critical bug where some switching points are missing
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2024-06-27 15:53:17 -07:00 |
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tangxifan
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5a7f618f29
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[core] debugging
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2024-06-27 15:44:17 -07:00 |
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tangxifan
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f4f487099d
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[core] syntax
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2024-06-27 15:07:48 -07:00 |
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tangxifan
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4185235a69
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[core] now clock routing is based on tree expansion. Unused part can be disconnected
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2024-06-27 15:02:20 -07:00 |
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tangxifan
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e75fd57af2
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[core] refactor codes
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2024-06-27 12:39:18 -07:00 |
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tangxifan
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7892c2340c
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[core] add a new option 'disable_unused_trees' to route clock rr graph
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2024-06-27 12:01:54 -07:00 |
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tangxifan
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6fceb81110
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[core] code format
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2024-06-27 10:19:40 -07:00 |
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tangxifan
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64a7a4ce26
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[core] syntax
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2024-06-27 10:19:14 -07:00 |
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tangxifan
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9ce552495a
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[core] now internal drivers can be routed in dedicated clock network
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2024-06-27 10:17:08 -07:00 |
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tangxifan
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ac1ad52795
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[core] code format
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2024-06-26 22:47:29 -07:00 |
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tangxifan
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5d0b0b9a8c
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[core] now global nets mapping are applied to clock routing
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2024-06-26 22:46:12 -07:00 |
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tangxifan
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d5d9531eec
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[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
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2024-06-26 21:52:45 -07:00 |
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tangxifan
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59be95b227
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[core] code format
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2024-06-26 17:58:26 -07:00 |
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tangxifan
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59404e5487
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[core] add verbose output
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2024-06-26 17:55:23 -07:00 |
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tangxifan
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576a861b8d
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[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
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2024-06-26 17:54:31 -07:00 |
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tangxifan
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3efa97b84e
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[core] support coordinate on clock taps
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2024-06-26 17:40:11 -07:00 |
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tangxifan
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fbece49047
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[core] fixed a bug where unexpected OPINs are added as internal drivers
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2024-06-25 12:07:19 -07:00 |
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tangxifan
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7bcbd8a88b
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[core] code format
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2024-06-25 11:44:50 -07:00 |
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tangxifan
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3b2c13402a
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[core] syntax
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2024-06-25 11:44:25 -07:00 |
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tangxifan
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31d4b4c402
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[core] now support add internal drivers to clock tree
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2024-06-25 11:27:22 -07:00 |
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tangxifan
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d2053db21c
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[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
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2024-06-21 19:00:01 -07:00 |
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tangxifan
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2193f108ee
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[core] add debugging messages
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2024-06-21 18:42:35 -07:00 |
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tangxifan
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3f08b83b3a
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[core] remove restrictions on 1 clock tree definition
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2024-06-21 17:12:10 -07:00 |
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tangxifan
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ecd31955b1
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[core] code format
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2024-06-21 17:11:32 -07:00 |
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tangxifan
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486cd01c15
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[core] now clock graph builder supports two types of switches
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2024-06-21 16:54:22 -07:00 |
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tangxifan
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ad8ad25250
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[core] format
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2024-05-31 19:44:40 -07:00 |
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tangxifan
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93ebbef851
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[core] fixed a bug
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2024-05-31 19:42:50 -07:00 |
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tangxifan
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514ec2f02e
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[core] code format
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2024-05-31 18:02:46 -07:00 |
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tangxifan
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2d10be9edb
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[core] code comments
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2024-05-31 18:00:24 -07:00 |
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tangxifan
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f9cd01636d
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[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
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2024-05-31 17:57:36 -07:00 |
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tangxifan
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212abecc27
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[core] syntax
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2024-05-31 17:41:49 -07:00 |
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tangxifan
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348d474bfd
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[core] more debuggin messages
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2024-05-31 17:40:19 -07:00 |
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tangxifan
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c565264e7d
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[core] more debuggin messages
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2024-05-31 17:14:42 -07:00 |
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tangxifan
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6dc31bf892
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[core] fixed a bug on missing net sync up during repack
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2024-05-31 16:53:59 -07:00 |
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tangxifan
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5b35f567d2
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[core] detailed messages to trace why some nets are no sync
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2024-05-31 16:00:10 -07:00 |
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tangxifan
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5adc1be204
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[core] syntax
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2024-05-31 15:50:27 -07:00 |
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tangxifan
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a9ccc277bd
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[core] more debugging message
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2024-05-31 15:49:34 -07:00 |
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tangxifan
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937e279c59
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[core] adding more debugging messages
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2024-05-31 15:43:51 -07:00 |
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tangxifan
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7a7fc679a8
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[core] enable more debugging message in repacker
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2024-05-31 14:52:59 -07:00 |
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tangxifan
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edb50f1b4d
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[core] update debug messages
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2024-05-31 14:37:46 -07:00 |
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tangxifan
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48c0b4b219
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[core] fixed a bug where net name is not shown correctly on wire LUTs
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2024-05-31 12:45:12 -07:00 |
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tangxifan
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74e94b855e
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[core] fixed a bug where gsb OPIN name does not match the switch block module
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2024-05-29 10:27:10 -07:00 |
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tangxifan
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52ae484a7c
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[core] fixed a bug on messed up wire connections for OPINs
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2024-05-20 13:50:31 -07:00 |
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tangxifan
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ca6e2f9831
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[core] code format
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2024-05-20 13:41:35 -07:00 |
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tangxifan
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4a791249bf
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[core] fixed a bug on requirement wire model for direction connection which is part of a cb
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2024-05-20 12:52:07 -07:00 |
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tangxifan
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b554a3d855
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[core] code format
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2024-05-19 17:24:38 -07:00 |
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tangxifan
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56aaa6a1f4
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[core] sytax
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2024-05-19 17:23:48 -07:00 |
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tangxifan
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065d77c679
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[core] supporting opin connection to cb in tiles
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2024-05-19 17:04:24 -07:00 |
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tangxifan
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9079056871
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[core] now connect OPIN to CB in top-level module
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2024-05-19 14:27:36 -07:00 |