tangxifan
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0f1ed19ad0
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Revert to the use of sprintf instead std::string. Have no idea why string is not working
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2019-06-07 18:54:57 -06:00 |
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tangxifan
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44ce0e8834
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update gsb unique module detection and fix formal verification port direction
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2019-06-07 17:18:38 -06:00 |
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tangxifan
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24d53390d8
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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tangxifan
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c9f810ceb6
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update rr_gsb to build connection blocks
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2019-06-07 11:01:55 -06:00 |
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tangxifan
|
472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
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ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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tangxifan
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8c1e7b799f
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fixed critical bugs in Connection Block Unique Module detection
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2019-06-06 16:31:50 -06:00 |
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tangxifan
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873e4d989f
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fine-tuning Verilog format and node addition to rr_blocks
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2019-06-06 12:48:41 -06:00 |
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tangxifan
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c2de0eefb1
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fix redundant comma in SB Verilog module
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2019-06-06 09:15:05 -06:00 |
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tangxifan
|
b9e1b1afc4
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fix a critical bug in num_reserved_sram_ports
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2019-06-05 17:31:01 -06:00 |
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tangxifan
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aaf8d23971
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fix critical bugs in routing submodules
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2019-06-05 16:43:18 -06:00 |
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tangxifan
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01e075377d
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fix typo in Verilog generation
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2019-06-05 15:30:34 -06:00 |
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tangxifan
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21d0cb52bc
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Merge remote-tracking branch 'origin' into tileable_sb
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2019-06-05 13:31:49 -06:00 |
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tangxifan
|
24ca3104b0
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fix minor bugs in Switch Block submodules
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2019-06-05 13:30:55 -06:00 |
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tangxifan
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0f87ae9886
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support switch block submodule Verilog generation by segments
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2019-06-05 12:56:05 -06:00 |
AurelienUoU
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84fabbd43b
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Fix sdc analysis bug related to virtual nodes + add the option in regression test
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2019-06-05 12:10:28 -06:00 |
Baudouin Chauviere
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d24488092d
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Fix bug
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2019-06-05 11:40:04 -06:00 |
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tangxifan
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c2d8fa00ba
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
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tangxifan
|
98b82c17be
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bug fixing for clear RRSwitchBlock
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2019-06-04 14:02:49 -06:00 |
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tangxifan
|
2c6780ab92
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add side mirror detection for RRSwitchBlock
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2019-06-04 13:01:22 -06:00 |
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Baudouin Chauviere
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1932d00309
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Correction of the SDC to remove global clocks
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2019-05-30 15:04:21 -06:00 |
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tangxifan
|
5b15a746d3
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add num_driver_nodes to Switch Block XML writter
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2019-05-28 20:52:33 -06:00 |
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tangxifan
|
5ed076dfb4
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fixed a critical bug in rotating
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2019-05-28 17:55:09 -06:00 |
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tangxifan
|
9cc5518d5a
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keep adding segment information for SB XML outputter
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2019-05-28 15:59:55 -06:00 |
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tangxifan
|
e7e18eb4c1
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Add more information in SB XML outputter
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2019-05-28 15:56:41 -06:00 |
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tangxifan
|
ca363da30c
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add options to specify output directory of SB XML
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2019-05-28 15:19:10 -06:00 |
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tangxifan
|
6b51b42ee7
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-28 14:53:44 -06:00 |
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tangxifan
|
af91fca1e0
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add rr_blocks XML writer to help debugging Switch Block Rotation
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2019-05-28 14:52:44 -06:00 |
|
Baudouin Chauviere
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3da216f297
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correction Null issue for the flat model
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2019-05-28 14:15:24 -06:00 |
|
tangxifan
|
6f30d3ad05
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support rotation on segment groups inside RRChan and improve rotatable mirror searching
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2019-05-28 11:25:16 -06:00 |
|
tangxifan
|
0f5666ea11
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fixed the bug in mirror node direction
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2019-05-27 21:58:21 -06:00 |
|
tangxifan
|
eece161d58
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keep debugging on Switch Block rotation
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2019-05-27 21:10:30 -06:00 |
|
tangxifan
|
5720217cfd
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Add copy constructor for RRChan, RRSwitchBlock etc.
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2019-05-27 15:44:34 -06:00 |
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tangxifan
|
1bea9870fc
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developed new rotating methods for RRSwitchBlocks, debugging ongoing
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2019-05-26 23:35:30 -06:00 |
|
tangxifan
|
4b852afeac
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skip rotating mirror detection which is too time-consuming
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2019-05-25 23:41:46 -06:00 |
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tangxifan
|
22e71f5847
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Add rotate one side of switch block functionality
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2019-05-25 22:48:07 -06:00 |
|
tangxifan
|
858a323228
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Add more support for rotating Switch Blocks
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2019-05-25 21:26:35 -06:00 |
|
tangxifan
|
2eab0b1c1c
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update unique_mirror search algorithm for Switch Blocks
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2019-05-25 19:54:15 -06:00 |
|
tangxifan
|
d3eae80e64
|
implemented an native way in finding rotable Switch blocks
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2019-05-25 19:37:18 -06:00 |
|
tangxifan
|
ae0248fbc6
|
debugging SwitchBlock rotating
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2019-05-24 23:10:30 -06:00 |
|
tangxifan
|
9adc2945c8
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add rotate functionality for RRSwitchBlock
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2019-05-24 21:40:16 -06:00 |
|
tangxifan
|
02b48d036d
|
clean warnings
|
2019-05-24 16:48:08 -06:00 |
|
tangxifan
|
2c46da6888
|
clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
|
tangxifan
|
27b996337a
|
fixed a critical bug in Compact Verilog generation for SB/CBs
|
2019-05-24 16:14:46 -06:00 |
|
tangxifan
|
1ade1f1d3f
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update SDC generator disabled_unused_mux by using RRSwitchBlock
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2019-05-24 15:42:00 -06:00 |
|
tangxifan
|
f27b88db8d
|
Use RRChan in SDC generator to replace old data structures
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2019-05-24 15:34:56 -06:00 |
|
tangxifan
|
27c234711e
|
clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
|
tangxifan
|
924136e7a2
|
Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
|
2019-05-24 15:10:08 -06:00 |
|
tangxifan
|
994b90ae53
|
updated report_timing for using RRSwitchBlock
|
2019-05-24 14:25:51 -06:00 |
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tangxifan
|
eef1312325
|
updated bitstream to use new RRSwitchBlock as well as the report timing engine
|
2019-05-24 12:54:10 -06:00 |