tangxifan
|
9cc9e45b4b
|
[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
|
2021-01-13 15:13:19 -07:00 |
Ashton Snelgrove
|
4efa5b98e8
|
Add docker distribution image.
|
2021-01-13 13:58:20 -07:00 |
|
tangxifan
|
91f12071d5
|
[Test] Use counter4bit in the multi-clock test
|
2021-01-13 13:34:59 -07:00 |
|
tangxifan
|
ccf3e037ff
|
[Benchmark] Change multi-clock counter from 8-bit to 4-bit
|
2021-01-13 13:31:06 -07:00 |
|
tangxifan
|
250adb01cf
|
[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
|
2021-01-13 13:18:31 -07:00 |
|
tangxifan
|
c0da6b900a
|
[Tool] Bug fix in creating multi-bit clock port connections
|
2021-01-12 18:38:00 -07:00 |
|
tangxifan
|
99e2a068fb
|
[Test] Add a test case for multi-clock
|
2021-01-12 18:06:25 -07:00 |
|
tangxifan
|
2f1aceda67
|
[Doc] Update documentation about architecture naming rules
|
2021-01-12 18:01:24 -07:00 |
|
tangxifan
|
9fa49c401c
|
[Arch] Add openfpga architecture which uses 4 global clocks
|
2021-01-12 18:00:22 -07:00 |
|
tangxifan
|
16b4e89326
|
[Doc] Update documentation for VPR architectures
|
2021-01-12 17:57:40 -07:00 |
|
tangxifan
|
7ccdff4543
|
[Arch] Add an architecture using 4 clocks
|
2021-01-12 17:55:57 -07:00 |
|
tangxifan
|
3790f2c26a
|
[Benchmark] Add 2-clock micro benchmark
|
2021-01-12 17:48:52 -07:00 |
|
tangxifan
|
a0b9f2b40d
|
Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
|
2021-01-11 10:02:31 -07:00 |
|
tangxifan
|
30aaab0c2e
|
[Test] Deploy new test to CI
|
2021-01-10 11:53:49 -07:00 |
|
tangxifan
|
65b2fe3ab7
|
[Tool] Bug fix in the global tile connection by considering all the subtiles
|
2021-01-10 11:52:38 -07:00 |
|
tangxifan
|
e58e1e86c2
|
[Test] Update test case to use new shell script
|
2021-01-10 11:09:10 -07:00 |
|
tangxifan
|
18d2a8ce19
|
[Flow] Add new script for fixed device layout using global tile clock
|
2021-01-10 11:08:02 -07:00 |
|
tangxifan
|
aaf582acc5
|
[Arch] Bug fix
|
2021-01-10 11:05:57 -07:00 |
|
tangxifan
|
1c68e43acf
|
[Test] Add new test case for registerable I/O architecture
|
2021-01-10 11:00:21 -07:00 |
|
tangxifan
|
f21d22f691
|
[Doc] Update README for new architectures
|
2021-01-10 10:54:59 -07:00 |
|
tangxifan
|
dfb3e32147
|
[Arch] Add openfpga archiecture for registerable I/O
|
2021-01-10 10:54:41 -07:00 |
|
tangxifan
|
853e7b1a40
|
[Arch] Add vpr architecture where I/O can be either combinational or registered
|
2021-01-10 10:54:09 -07:00 |
|
tangxifan
|
43418cd76b
|
[Test] Deploy pipeplined and2 to test cases
|
2021-01-10 10:28:22 -07:00 |
|
tangxifan
|
6521aa2e7a
|
[Benchmark] Bug fix in pipelined and2 benchmark
|
2021-01-10 10:27:59 -07:00 |
|
tangxifan
|
4412bbd084
|
[Benchmark] Add a micro benchmark to test pipelined architecture
|
2021-01-10 10:21:30 -07:00 |
|
tangxifan
|
0c808bec41
|
[Doc] Add clarification for defining multi-bit global tile ports
|
2021-01-09 20:00:16 -07:00 |
|
tangxifan
|
4124777948
|
[Tool] Set (x,y) to be optional XML syntax in tile annotation
|
2021-01-09 18:56:41 -07:00 |
|
tangxifan
|
2324edc522
|
[Doc] Update documentation for upgraded tile annotation
|
2021-01-09 18:55:16 -07:00 |
|
tangxifan
|
9a441fa5cc
|
[Tool] Upgrade openfpga to support extended global tile port definition
|
2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
0b74575606
|
[Arch] Update arch using global reset tile port
|
2021-01-09 18:04:55 -07:00 |
|
tangxifan
|
7b24da267a
|
[Arch] Remove port size XML syntax
|
2021-01-09 16:30:46 -07:00 |
|
tangxifan
|
9f12b25a24
|
[Arch] Add port size to global port defined thru tile annotation
|
2021-01-09 16:23:28 -07:00 |
|
tangxifan
|
0f5f0a3527
|
[Arch] Add x,y coordinates to global port definition
|
2021-01-09 15:50:09 -07:00 |
|
tangxifan
|
a14a56772a
|
[Arch] Introduce new XML syntax for global port in tile annotation
|
2021-01-09 15:48:42 -07:00 |
|
tangxifan
|
e86a929154
|
Merge pull request #168 from lnis-uofu/yosys_bump_submodule
Bumping yosys submodule with the latest changes done in yosys repo re…
|
2021-01-09 13:32:30 -07:00 |
Lalit Sharma
|
8a5741b1ae
|
Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
|
2021-01-08 07:08:24 -08:00 |
|
tangxifan
|
0bb1f92ed8
|
Merge pull request #167 from lnis-uofu/dev
Support on Using Scan-chain Flip-flop in Configuration Chain
|
2021-01-07 10:00:34 -07:00 |
|
tangxifan
|
cde26597ed
|
[Tool] Bug fix in scan chain builder calling
|
2021-01-04 18:45:47 -07:00 |
|
tangxifan
|
226f6b8d6d
|
[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
|
2021-01-04 18:30:04 -07:00 |
|
tangxifan
|
62eb6e24cb
|
[Test] Add SCFF configuration chain test case to CI
|
2021-01-04 17:42:49 -07:00 |
|
tangxifan
|
804b721a19
|
[Tool] Bug fix in the configuration chain connection builder
|
2021-01-04 17:41:29 -07:00 |
|
tangxifan
|
a813c9016b
|
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
|
2021-01-04 17:39:13 -07:00 |
|
tangxifan
|
06af30ef10
|
[Test] Add test case for the SCFF usage in configuration chain
|
2021-01-04 17:30:19 -07:00 |
|
tangxifan
|
bfd305b5a5
|
[Tool] Patch the bug in finding data output ports for CCFF
|
2021-01-04 17:22:30 -07:00 |
|
tangxifan
|
709ee1b842
|
[HDL] Update dff netlist for SCFF used in configuration chain
|
2021-01-04 17:17:35 -07:00 |
|
tangxifan
|
c97a92d628
|
[Arch] Patch openfpga architecture for ccff circuit model port requirement
|
2021-01-04 17:15:50 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
cb34be0dc0
|
[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
|
2021-01-04 15:13:54 -07:00 |
|
tangxifan
|
294ad97d38
|
[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
|
2021-01-04 14:56:49 -07:00 |
|
tangxifan
|
722a9bcf63
|
[HDL] Add scan-chain DFF cell with configuration enable signal
|
2021-01-04 14:31:26 -07:00 |