tangxifan
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8b8e18a8de
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bug fixing for mux subckt names
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2019-07-17 08:59:57 -06:00 |
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tangxifan
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a2505ff16a
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turn on std cell explicit port map
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2019-07-17 08:36:09 -06:00 |
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tangxifan
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dcc96bf7f5
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bug fixing
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2019-07-17 08:25:52 -06:00 |
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tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
AurelienUoU
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8b7f20f1ba
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Merge branch 'dev' into documentation
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2019-07-17 07:33:30 -06:00 |
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AurelienUoU
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5b8eaab93f
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Docker test 2.3
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2019-07-16 20:13:46 -06:00 |
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tangxifan
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4672311aae
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Merge pull request #13 from LNIS-Projects/dev
Dev
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2019-07-16 22:10:04 -04:00 |
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AurelienUoU
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ca2c840e1e
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Docker test 2.2
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2019-07-16 20:04:04 -06:00 |
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AurelienUoU
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b31fb0ab83
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Docker test 2.1
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2019-07-16 19:56:13 -06:00 |
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AurelienUoU
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31e6ee3ee1
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Docker test 2
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2019-07-16 19:47:53 -06:00 |
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AurelienUoU
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1822e2059a
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Docker building test
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2019-07-16 19:32:06 -06:00 |
AurelienAlacchi
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3aa0a4a5e6
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Merge pull request #12 from LNIS-Projects/tangxifan-patch-1
Update building.md
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2019-07-16 21:20:38 -04:00 |
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tangxifan
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d6dfc29508
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Now we use the ace from VTR
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2019-07-16 17:00:09 -06:00 |
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AurelienUoU
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938f2ec68c
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Update Dockerfile
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2019-07-16 16:30:00 -06:00 |
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tangxifan
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61026dc623
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Update building.md
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2019-07-16 16:58:11 -04:00 |
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tangxifan
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954a8c14f7
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remove redundant files
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2019-07-16 14:55:04 -06:00 |
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tangxifan
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da8745b163
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Update README.md
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2019-07-16 16:51:52 -04:00 |
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tangxifan
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0c68642aad
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Update README.md
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2019-07-16 16:49:15 -04:00 |
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tangxifan
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e9154b1f74
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 14:42:45 -06:00 |
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tangxifan
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b807fdb38a
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Merge branch 'tileable_routing' into dev
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2019-07-16 14:38:18 -06:00 |
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tangxifan
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be255edc68
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now use vtr_assert in ace
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2019-07-16 14:37:19 -06:00 |
Baudouin Chauviere
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712eccfa30
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Merge branch 'dev', remote-tracking branch 'origin' into explicit_verilog
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2019-07-16 13:37:52 -06:00 |
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Baudouin Chauviere
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65122d04b3
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:37:21 -06:00 |
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tangxifan
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115411941b
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-16 13:15:45 -06:00 |
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AurelienUoU
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509c1d2c80
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Link path correction
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2019-07-16 13:13:58 -06:00 |
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Baudouin Chauviere
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69014704ef
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Explicit verilog final push
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2019-07-16 13:13:30 -06:00 |
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AurelienAlacchi
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b0017cdbdf
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Merge pull request #11 from LNIS-Projects/dev
Dev
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2019-07-16 13:08:24 -06:00 |
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Baudouin Chauviere
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e602006a07
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-16 12:45:13 -06:00 |
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AurelienUoU
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fe218fc207
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Tutorial update
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2019-07-16 11:52:24 -06:00 |
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AurelienUoU
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a04555419a
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Typo fix
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2019-07-16 07:30:25 -06:00 |
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AurelienUoU
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3d079c9421
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Add folder creation in tuto_fpga_flow.sh to ease the use
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2019-07-16 07:20:21 -06:00 |
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AurelienUoU
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b810b5cab9
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fpga_flow bug fix + upload k8 architecture
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2019-07-16 07:04:45 -06:00 |
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AurelienUoU
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35e1962732
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Merge branch 'dev' into documentation
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2019-07-15 21:19:26 -06:00 |
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AurelienUoU
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1cf4e78502
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Update documentation and help
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2019-07-15 21:16:15 -06:00 |
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tangxifan
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bcc6346533
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speeding up identifying unique modules in routing
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2019-07-14 13:49:20 -06:00 |
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tangxifan
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4c6e245885
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speed-up the unique routing process
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2019-07-14 12:22:00 -06:00 |
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tangxifan
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b690e702f6
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adding more info to show the progress bar in backannotating GSBs
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2019-07-13 19:53:44 -06:00 |
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tangxifan
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aa4cd850ae
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try to optimize the runtime of routing uniqueness detection
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2019-07-13 18:10:34 -06:00 |
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tangxifan
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78578f66c5
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bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
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2019-07-13 14:48:32 -06:00 |
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AurelienUoU
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1a5c5ff4a6
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Update demo simulation result path
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2019-07-12 16:52:54 -06:00 |
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AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
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AurelienUoU
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ef600bc63f
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Save workspace
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2019-07-12 15:57:41 -06:00 |
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AurelienUoU
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d10cc34c9e
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Update Readme and tutorial
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2019-07-12 14:56:08 -06:00 |
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Baudouin Chauviere
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f140e08093
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Pre-Merge modifications
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2019-07-12 10:48:43 -06:00 |
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Baudouin Chauviere
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a0f1f8d163
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Fix when explicit verilog is NOT used
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2019-07-12 10:39:31 -06:00 |
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tangxifan
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f0ecc51b51
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bug fixing to resolve the conflicts between explicit port map and standard cell map
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2019-07-12 10:38:20 -06:00 |
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AurelienUoU
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e65cf9f5fd
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Update ERI-demo
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2019-07-12 08:55:19 -06:00 |
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Baudouin Chauviere
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40d3460bac
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:30 -06:00 |
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Baudouin Chauviere
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29ffa1cdcb
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
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2019-07-11 22:13:09 -06:00 |
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Baudouin Chauviere
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e461cd0b99
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Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
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2019-07-11 22:09:49 -06:00 |