tangxifan
|
86e7c963f8
|
[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
|
2021-10-02 22:19:20 -07:00 |
|
tangxifan
|
0b06820177
|
[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
|
2021-10-01 17:06:35 -07:00 |
|
tangxifan
|
7ba5d27ea7
|
[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
|
2021-10-01 17:02:35 -07:00 |
|
tangxifan
|
ff6f7e80f6
|
[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
|
2021-10-01 16:52:06 -07:00 |
|
tangxifan
|
dda147e234
|
[Flow] Add an example simulation setting file for defining programming shift register clocks
|
2021-10-01 11:04:23 -07:00 |
|
tangxifan
|
7b010ba0f4
|
[Engine] Support programming shift register clock in XML syntax
|
2021-10-01 11:00:38 -07:00 |
|
tangxifan
|
fa57117f50
|
[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
|
2021-10-01 10:19:51 -07:00 |
|
tangxifan
|
41cc375746
|
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
|
2021-09-29 16:34:40 -07:00 |
|
tangxifan
|
89a97d83bd
|
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
|
2021-09-29 16:28:06 -07:00 |
|
tangxifan
|
4968f0d11f
|
Merge branch 'master' into qlbank_sr
|
2021-09-28 14:20:30 -07:00 |
|
tangxifan
|
80232fc459
|
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
|
2021-09-28 12:36:36 -07:00 |
|
tangxifan
|
4c04c0fbd7
|
[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
|
2021-09-28 12:35:42 -07:00 |
|
tangxifan
|
2ce2fb269a
|
[HDL] Added a different FF model which is designed to drive WLW only
|
2021-09-28 12:35:13 -07:00 |
|
tangxifan
|
6469ee3048
|
[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
|
2021-09-28 12:21:54 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
4aed045cdd
|
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
|
2021-09-28 11:34:20 -07:00 |
|
tangxifan
|
811c898173
|
[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
|
2021-09-28 11:29:45 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
|
2021-09-28 11:27:49 -07:00 |
|
tangxifan
|
1ca1b0f3e9
|
[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
|
2021-09-22 15:58:05 -07:00 |
|
tangxifan
|
655b195d8b
|
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
|
2021-09-22 15:56:44 -07:00 |
|
tangxifan
|
a98df811ed
|
[Arch] Bug fix: wrong circuit model name was used for CCFF
|
2021-09-22 15:50:47 -07:00 |
|
tangxifan
|
53da5d49fe
|
[Arch] Correct XML syntax errors
|
2021-09-22 15:48:14 -07:00 |
|
tangxifan
|
3cfd5c3531
|
[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
|
2021-09-22 15:04:59 -07:00 |
|
tangxifan
|
212c5bd642
|
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
|
2021-09-22 15:04:19 -07:00 |
|
tangxifan
|
b0aaab9c03
|
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
|
2021-09-22 11:32:13 -07:00 |
|
tangxifan
|
efed268585
|
[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
|
2021-09-22 11:30:08 -07:00 |
|
tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
|
2021-09-22 11:27:09 -07:00 |
|
tangxifan
|
337ed33b68
|
[Test] Added a sample fabric key for 2-region QL memory bank
|
2021-09-22 11:25:16 -07:00 |
|
tangxifan
|
7db7e2d8f6
|
[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
|
2021-09-22 10:05:27 -07:00 |
|
tangxifan
|
d0fe12fadd
|
[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
|
2021-09-22 10:03:39 -07:00 |
|
tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
|
2021-09-22 10:01:33 -07:00 |
|
tangxifan
|
ab42239b94
|
[Test] Bug fix in the fabric key
|
2021-09-21 16:44:58 -07:00 |
|
tangxifan
|
f57aceff87
|
[Test] Deploy the load external key test case for ql memory bank to basic regression tests
|
2021-09-21 16:25:14 -07:00 |
|
tangxifan
|
aad47ffbc6
|
[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
|
2021-09-21 16:22:50 -07:00 |
|
tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
|
tangxifan
|
cd0d8b86fa
|
[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
|
2021-09-21 15:55:34 -07:00 |
|
tangxifan
|
7327850cf3
|
[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
|
2021-09-21 15:43:54 -07:00 |
|
tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
|
tangxifan
|
d36d1ebee2
|
[HDL] Temporarily disable WLR func in primitive HDL modeling
|
2021-09-20 17:07:51 -07:00 |
|
tangxifan
|
0450d57d82
|
[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
|
2021-09-20 16:05:01 -07:00 |
|
tangxifan
|
3f6ac41868
|
[Test] Deploy the WLR test to the basic regression tests
|
2021-09-20 11:21:58 -07:00 |
|
tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
|
2021-09-20 11:20:36 -07:00 |
|
tangxifan
|
5c1c428ea5
|
[HDL] Updated cell library with the SRAM cell with Read Enable signal
|
2021-09-20 11:13:36 -07:00 |
|
tangxifan
|
cd2978a434
|
[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
|
2021-09-20 11:13:02 -07:00 |
|
tangxifan
|
81a2ad58df
|
[Test] Deploy the ql memory bank test case to basic regression tests (run on CI)
|
2021-09-09 13:48:30 -07:00 |
|
tangxifan
|
b82cfdf555
|
[Test] Add the QL memory bank test to regression test cases
|
2021-09-09 09:29:21 -07:00 |
|
tangxifan
|
6be3c64f1c
|
[Arch] Add an example architecture using the physical design friendly memory bank organization
|
2021-09-09 09:22:27 -07:00 |
|
tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
|
2021-09-01 14:19:00 -07:00 |
Will
|
c31c1d8b04
|
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
|
2021-08-13 11:08:09 -04:00 |
|
tangxifan
|
9f03ecb160
|
[Test] Patch test case due to the changes in counter benchmarks
|
2021-07-02 17:57:39 -06:00 |