Lin
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75710f8c8a
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add warning in doc
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2024-11-01 10:54:58 +08:00 |
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Lin
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539e37118a
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add option reduce error to warning
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2024-10-31 10:47:26 +08:00 |
tangxifan
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af09120a52
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[doc] update fig
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2024-09-21 13:35:42 -07:00 |
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tangxifan
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26cda624d3
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[doc] add new syntax about clock network
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2024-09-21 13:31:30 -07:00 |
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tangxifan
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4905e694ab
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[doc] typo
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2024-09-18 21:59:06 -07:00 |
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tangxifan
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1789ce06c4
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[doc] update new syntax with example
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2024-09-18 17:55:05 -07:00 |
Jingrong Lin
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b5452b7a3c
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Merge branch 'master' into preloading_clean
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2024-09-14 10:54:14 +08:00 |
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Lin
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423e15289c
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add link to command doc, valid now
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2024-09-12 13:47:10 +08:00 |
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Lin
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52f5cf0399
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add link to command doc
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2024-09-12 13:36:06 +08:00 |
Victor
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e5b3f5d90c
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add link to file format description page
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2024-09-12 12:48:00 +08:00 |
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Lin
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e6c43ec9ad
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add command doc
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2024-09-12 11:41:52 +08:00 |
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Victor
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7f88e97514
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refine doc format
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2024-09-12 10:33:06 +08:00 |
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Victor
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22da608e05
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add ident
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2024-09-12 09:58:13 +08:00 |
|
Victor
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65e38e5f91
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update document format
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2024-09-11 19:27:03 +08:00 |
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Lin
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27db6d2496
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modified unique_block.rst
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2024-09-11 18:28:32 +08:00 |
|
Lin
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172260e2fb
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modified index.rst
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2024-09-11 18:17:45 +08:00 |
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Jingrong Lin
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77b188060b
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Merge branch 'master' into preloading_clean
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2024-09-11 11:08:49 +08:00 |
victorzh001
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04a60ca4b5
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Merge branch 'master' into victor_OpenFPGA_dbg
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2024-09-10 11:01:47 +08:00 |
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Victor
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3ea830e168
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Add the reference_file to the index.rst
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2024-09-10 10:46:15 +08:00 |
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tangxifan
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3b1f51b9d9
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[doc] add new options
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2024-09-09 13:46:58 -07:00 |
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Victor
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8d97ebd980
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Add more test cases and update documentation about the YAML file format of this command
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2024-09-09 17:49:10 +08:00 |
|
Victor
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7bacc781d0
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update code according to code review comments
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2024-09-06 15:39:08 +08:00 |
|
Jingrong Lin
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263eb6b7fb
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Update unique_blocks.rst
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2024-09-04 15:14:41 +08:00 |
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Lin
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a70582c6c4
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preload document copied
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2024-09-04 14:45:41 +08:00 |
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tangxifan
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e7ab7a61f1
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[doc] update to use tile name and index when defining clock taps
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2024-08-09 18:09:12 -07:00 |
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tangxifan
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85c9bdc6f9
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[doc] add new format
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2024-08-06 17:28:03 -07:00 |
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tangxifan
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c11a2c7381
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[doc] format to resolve latexpdf build errors; now local build passes
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2024-08-03 15:03:14 -07:00 |
chungshien-chai
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22d7df5ffb
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Update doc
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2024-07-28 02:40:24 -07:00 |
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chungshien-chai
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cbe9a46f95
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Format and update doc
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2024-07-28 00:02:20 -07:00 |
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chungshien-chai
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0ff0c3445e
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Update doc
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2024-07-26 13:43:31 -07:00 |
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tangxifan
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0c99fcf6f4
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[doc] format
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2024-07-10 15:07:57 -07:00 |
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tangxifan
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a390aad0b8
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[doc] add new syntax
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2024-07-10 15:07:16 -07:00 |
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tangxifan
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f42884304a
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[doc] update clock network details
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2024-07-09 11:40:41 -07:00 |
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tangxifan
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bf484dbc70
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[doc] add perimeter cb examples on prog clk network
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2024-07-08 21:25:12 -07:00 |
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tangxifan
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229adebe07
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[doc] new option to write_fabric_verilog
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2024-07-08 21:06:12 -07:00 |
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tangxifan
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8a5c33b1d6
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[doc] new option for perimeter cb
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2024-07-08 19:01:16 -07:00 |
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tangxifan
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4da5150a26
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[doc] update for bottom-left tile organization
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2024-07-07 14:20:26 -07:00 |
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tangxifan
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91f8bb5841
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[doc] update figures for ecb
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2024-07-07 13:40:01 -07:00 |
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tangxifan
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e3a258a5ab
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[doc] typo
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2024-07-02 19:31:45 -07:00 |
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tangxifan
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ec7ca1add1
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[doc] add example to example clock network
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2024-07-01 21:41:33 -07:00 |
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tangxifan
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18e2b994ac
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[doc] update syntax on clock network file
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2024-06-30 22:56:31 -07:00 |
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tangxifan
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1094af9f73
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[doc] add new options to route clock graph
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2024-06-28 12:38:40 -07:00 |
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tangxifan
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3fb891094b
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[doc] add new syntax
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2024-06-27 11:02:37 -07:00 |
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tangxifan
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ec1ad94d4a
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[doc] add syntax about internal drivers
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2024-06-25 13:06:47 -07:00 |
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tangxifan
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253e3e0cba
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[doc] add new syntax for clock network
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2024-06-23 17:43:38 -07:00 |
|
tangxifan
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87a07fb111
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[doc] add missing links
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2024-06-10 10:57:27 -07:00 |
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tangxifan
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e6784fdf6c
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[doc] merge cicd into ci section
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2024-06-10 10:47:22 -07:00 |
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tangxifan
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3955c80257
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[doc] now add tips/notes to readme. Update broken links
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2024-06-10 10:42:29 -07:00 |
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tangxifan
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b491ba03b7
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[doc] typo
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2024-05-29 10:33:39 -07:00 |
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tangxifan
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391b768b3a
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[doc] syntax
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2024-05-21 11:14:12 -07:00 |