tangxifan
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953625b1ca
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[core] format
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2023-03-05 22:32:05 -08:00 |
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tangxifan
|
de1e300ec7
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[core] now resize rr_node for clock graph is working
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2023-03-05 22:21:55 -08:00 |
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tangxifan
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81e9187aac
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[core] debugging
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2023-03-03 22:55:14 -08:00 |
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tangxifan
|
4423d917fa
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[core] debugging
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2023-03-03 18:00:43 -08:00 |
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tangxifan
|
29ee6e7136
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[core] debugging
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2023-03-03 17:33:53 -08:00 |
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tangxifan
|
98d8c75d86
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[code] format
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2023-03-02 21:36:08 -08:00 |
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tangxifan
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02b50e3464
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[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
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2023-03-02 21:33:32 -08:00 |
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tangxifan
|
46510388be
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[core] now fabric generator can wire clock ports to routing blocks
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2023-03-02 12:33:26 -08:00 |
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tangxifan
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099d9f32f4
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[core] dev
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2023-03-01 16:08:15 -08:00 |
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tangxifan
|
2ff8fb8737
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[core] wrapping up clock routing command
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2023-02-28 16:52:54 -08:00 |
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tangxifan
|
8d5c21b14d
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[core] code format
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2023-02-27 23:00:15 -08:00 |
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tangxifan
|
2735b708d3
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[core] reworked the tapping XML syntax
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2023-02-27 22:59:44 -08:00 |
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tangxifan
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ff69664c14
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[core] syntax
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2023-02-27 22:39:12 -08:00 |
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tangxifan
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d4e19edc71
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[core] finishing up clock rr_graph appending
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2023-02-27 22:31:16 -08:00 |
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tangxifan
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9f20d2e639
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[lib] now clock arch supports tap points
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2023-02-27 22:06:13 -08:00 |
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tangxifan
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3a40c5e15f
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[lib] update example of clock arch definition
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2023-02-27 21:49:14 -08:00 |
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tangxifan
|
7d0c23c675
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[lib] new api for lowest level clock connections
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2023-02-27 15:16:23 -08:00 |
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tangxifan
|
b3dec93eb9
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[core] code format
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2023-02-27 15:12:59 -08:00 |
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tangxifan
|
9ec4d690db
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[core] clock edges interconnecting clock tracks across levels
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2023-02-27 15:10:36 -08:00 |
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tangxifan
|
b6eace8fac
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[core] now switch id is linked in clock network
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2023-02-27 13:10:54 -08:00 |
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tangxifan
|
009d711ba5
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[core] code format
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2023-02-26 22:23:41 -08:00 |
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tangxifan
|
87a9146082
|
[core] adding rr spatial lookup for clock nodes only
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2023-02-26 22:23:17 -08:00 |
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tangxifan
|
db36f87dfa
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[core] enhance clock tree arch validation
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2023-02-26 18:39:53 -08:00 |
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tangxifan
|
780fc0f26d
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[core] developing validators and annotate rr_segment for clock arch
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2023-02-26 18:03:55 -08:00 |
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tangxifan
|
75773ddd4e
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[code] format
|
2023-02-26 12:46:29 -08:00 |
|
tangxifan
|
3db5acfb37
|
[core] dev
|
2023-02-26 12:40:13 -08:00 |
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tangxifan
|
8f0d94ba73
|
[code] format
|
2023-02-25 22:43:21 -08:00 |
|
tangxifan
|
0b33650761
|
[core] dev
|
2023-02-25 22:41:33 -08:00 |
|
tangxifan
|
7f07a9d031
|
[lib] add default seg/switch to clock arch. Fixed syntax
|
2023-02-24 19:15:39 -08:00 |
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tangxifan
|
65b27a3377
|
[lib] fixed a few bugs
|
2023-02-22 21:29:18 -08:00 |
|
tangxifan
|
40f6b5a3fe
|
[lib] fixed a few bugs
|
2023-02-22 21:23:08 -08:00 |
|
tangxifan
|
a9d5e4dfbd
|
[lib] update example clock arch xml
|
2023-02-22 21:18:00 -08:00 |
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tangxifan
|
d1133000ba
|
[lib] code format
|
2023-02-22 21:03:04 -08:00 |
|
tangxifan
|
aafd1e6fb3
|
[lib] syntax
|
2023-02-22 21:02:35 -08:00 |
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tangxifan
|
b2ef1db5f4
|
[lib] finishing up code changes; start debugging
|
2023-02-22 20:46:18 -08:00 |
|
tangxifan
|
1c8a5eb098
|
[lib] adding linker
|
2023-02-22 20:29:32 -08:00 |
|
tangxifan
|
bf2876c60e
|
[lib] developing linker
|
2023-02-22 18:36:22 -08:00 |
|
tangxifan
|
ce20a16aad
|
[lib] adding unit test
|
2023-02-22 18:26:18 -08:00 |
|
tangxifan
|
b37deb4b02
|
[lib] adding writer
|
2023-02-22 18:21:28 -08:00 |
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tangxifan
|
5cd310c4cc
|
[lib] adding missing apis
|
2023-02-22 15:04:52 -08:00 |
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tangxifan
|
7bc843b74a
|
[lib] developing xml parser for clk arch
|
2023-02-22 13:23:09 -08:00 |
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tangxifan
|
25e43b47da
|
[lib] first round of data structure on clock arch
|
2023-02-22 12:18:44 -08:00 |
|
tangxifan
|
9eb2374bc6
|
[lib] developing
|
2023-02-21 22:29:25 -08:00 |
|
tangxifan
|
fe594acab1
|
[lib] adding clock network data structure
|
2023-02-21 16:53:05 -08:00 |
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tangxifan
|
e7fc065032
|
[lib] start developing clock arch data structure and I/O
|
2023-02-21 15:06:35 -08:00 |