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Author SHA1 Message Date
Tim Newsome 3839cbf0ad Add some error checking to examine(). 
Fixes #183.

Change-Id: I6fb45adf4c97ea339c9d4ca3b372a09b18e3b56e
 2018-01-19 13:58:02 -08:00
Tim Newsome 7f368468c8 Remove dead code. 
Change-Id: Ic90598b3dd4128dabb18ac4dc1285ca721a6a441
 2018-01-15 12:07:20 -08:00
Megan Wachs 6f9585068f
Merge pull request #172 from riscv/dbus_read_comment 
Add a comment in dbus_read
 2018-01-10 15:30:56 -08:00
Tim Newsome 0d60a29c21
Merge pull request #178 from riscv/cleanup 
Rename dummy variable to be correct.
 2018-01-10 15:16:40 -08:00
Tim Newsome 29c7a76708 Muck with mstatus to always be able to read FPRs 
Change-Id: I7ff8bde4578c9ddd175c5cca370295c790cfbba7
 2018-01-09 12:06:11 -08:00
Tim Newsome fd506fa839 Propagate register read errors. 
Change-Id: Idda111377873a2236b5b91e4ffdabd2be384b47a
 2018-01-08 11:53:02 -08:00
Tim Newsome 0e3869cbf6
Merge pull request #179 from riscv/multicore_hart_selection 
Select current hart before reading memory.
 2018-01-05 14:07:38 -08:00
Tim Newsome 11e51af3b1
Merge pull request #173 from riscv/warn_names 
Use register names instead of numbers in warnings
 2018-01-05 13:07:08 -08:00
Tim Newsome 37434ffd77 Rename dummy variable to be correct. 
Change-Id: I329404894227bb3cf563382e1adf0edda702543b
 2018-01-05 13:05:33 -08:00
Tim Newsome 6f3913cedc Select current hart before reading memory. 
This avoids trying to read memory from the wrong hart, if the current
hart was changed by an earlier call (eg. to poll()).

Change-Id: I73da1e01c8d01d68f01ac7fdd6c548380a70cfd3
 2018-01-04 17:12:01 -08:00
Tim Newsome 097d62d159 Make delay update messages debug instead of info. 
They confuse users otherwise.

Change-Id: I3bc491352f5384e36c54696a0ecbf11ac623dd83
 2018-01-04 13:36:53 -08:00
Megan Wachs 33aad3524b
Add a comment in dbus_read 
This just comments the current behavior
 2018-01-04 13:27:35 -08:00
Tim Newsome 07e19e17cb Use register names instead of numbers in warnings 
Change-Id: Ie2295d30fd9dfeb7590f5e34d572497a93a3ce7b
 2018-01-04 13:27:18 -08:00
Tim Newsome 365c79c3ff Get rid of abort() calls. 
Also changed a few asserts that could trigger due to broken hardware.

Fixes Issue #142.

Change-Id: Ia2b99baa82f30ebcb2fd7e4902f0e67046ce4ed2
 2017-12-27 13:45:50 -08:00
Tim Newsome 06445f5743 Propagate error instead of calling abort(). 
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.

Partly addresses Issue #142

Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
 2017-12-26 15:04:02 -08:00
Tim Newsome 4fa3d819d2 Remove unused code. 
Change-Id: Ibc72945ac76513c84d62616c0210e6013b21f7ef
 2017-12-26 14:27:44 -08:00
Tim Newsome d942bce996 Conform to OpenOCD style guide. 
Change-Id: I2b23ac79639ed40e9d59db5c52ea2196df0349bc
 2017-12-26 11:38:11 -08:00
Tim Newsome 1f66c7827b Fix flash/run algorithm with new register names 
Change-Id: I8f539c880ee5da864956f56943411b228d8a5812
 2017-12-21 16:41:50 -08:00
Megan Wachs 33ef457c6a
Merge pull request #155 from riscv/debug_defines 
Update debug_defines to the one used with spike.
 2017-12-21 15:17:43 -08:00
Megan Wachs a81ad34af3
Merge pull request #148 from riscv/macbuild 
Use %ll instead of %L in scanf.
 2017-12-21 15:16:57 -08:00
Tim Newsome 5892b26259 Update debug_defines to the one used with spike. 
Change-Id: I627c6ee557d98239227324c33f9b89f6280cbf93
 2017-12-21 15:05:12 -08:00
Tim Newsome fa385bdcd5 Use parens after if. 
I'm surprised this built with gcc before.

Fixes Issue #150.

Change-Id: I24d2957783c66ad53d5b532a4e930349a2059a97
 2017-12-21 12:43:22 -08:00
Tim Newsome 11c261cd50 Add `riscv expose_csrs` command. 
This lets users tell OpenOCD which non-standard CSRs exist on their
target, that will also be accessible and whose existence will be
communicated to gdb.

Change-Id: I56163a9fcb84ad7ebe815ae74fbd9fcc208f5a9d
 2017-12-19 10:41:48 -08:00
Tim Newsome 5f86f7208d Hide supervisor registers if there is no S mode. 
Also update encoding.h.

Change-Id: I275be7de0aa1af64d13ea191b9f4ff391cfb16dc
 2017-12-19 10:41:48 -08:00
Tim Newsome f55d1a2030 Give FPRs ABI names. 
Change-Id: If198d10e16671b9868836e23386aaf8d4b05f317
 2017-12-19 10:41:48 -08:00
Tim Newsome c7cddd2b5c Remove some debug printfs. 
Change-Id: I09989d4c0e102889ecb0eedbd3f4138f8b7bdb8c
 2017-12-19 10:41:48 -08:00
Tim Newsome 56ad0e5b30 Avoid another assertion failure. 
Change-Id: Ia54f778152974164697b712c360918e17a127d95
 2017-12-19 10:41:48 -08:00
Tim Newsome 10c17fdf17 Read misa before using it to check for extensions. 
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
 2017-12-19 10:41:48 -08:00
Tim Newsome ec1c814017 Don't rely on hart count until it's correct. 
Change-Id: I4e05eb091823b2e0fb481ca0b599072ba1ca70f2
 2017-12-19 10:41:48 -08:00
Tim Newsome 46715c7d8a Remove no-longer-true comment. 
Change-Id: I888680e73682582438a0de0496238867f1604754
 2017-12-19 10:41:48 -08:00
Tim Newsome 120477b2a2 Simplify examine() 
Now we don't have to play tricks fooling other parts of our code that
might assert.

Change-Id: Ia574378e1f95ed62d297e6b2e852245e58c9ffc9
 2017-12-19 10:41:48 -08:00
Tim Newsome 37278cf2ec Make priv register 8 bits. 
(It's really only 2 bits, but something wonky happens between gdb and
OpenOCD if I make it that size.)

Change-Id: I562a65cb0ebe5aa0edcc54c251d0fea0e26f9cb1
 2017-12-19 10:41:48 -08:00
Tim Newsome f341db9f72 WIP xml register for 0.11. 
On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.

Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
 2017-12-19 10:41:48 -08:00
Tim Newsome 8926e66d3a Hide unknown registers, which probably don't exist 
Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
 2017-12-19 10:41:48 -08:00
Tim Newsome 26a54452d2 Fix register names. 
Use the ABI ones for every register that we have one for.

Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
 2017-12-19 10:41:48 -08:00
Tim Newsome 7c989698a1 WIP better CSR names, and include only existing 
Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
 2017-12-19 10:41:48 -08:00
Tim Newsome a5cb0b2270 WIP. Hide FPRs if the hart doesn't support F/D. 
Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
 2017-12-19 10:41:48 -08:00
Tim Newsome e648856a41 `make all` debug tests now pass. 
Also properly support (I think) D extension on RV32.

Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
 2017-12-19 10:41:48 -08:00
Tim Newsome c421fefdcb Checkpoint that seems to work. 
Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
 2017-12-19 10:41:48 -08:00
Tim Newsome 1e43d32e01 Use %ll instead of %L instead of scanf. 
Mac build barfs on L, and the manpage says they're equivalent.

Hopefully fixes #147

Change-Id: I3aa57775731f3f5ceb03097cae2a9dc6fd426dcd
 2017-12-15 15:31:36 -08:00
Tim Newsome 6aff46adcc Fix cut and paste bug. 
Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.

Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
 2017-12-14 13:51:13 -08:00
Tim Newsome 0a65a6527d Fix build. 
Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
 2017-12-11 12:58:20 -08:00
Tim Newsome e50ee46a6f
Merge pull request #131 from riscv/small_progbuf 
Support program buffers that are just 2 instructions large
 2017-12-11 12:52:31 -08:00
Tim Newsome 4d5f74fbe6 Update encoding.h. 
Change-Id: Id653500aa525746e8824ff5fd2850c62c8c21c08
 2017-11-27 13:23:33 -08:00
Tim Newsome 52cdf286ca Add missing return. 
Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
 2017-11-16 15:58:08 -08:00
Tim Newsome e28abf7c9e Merge branch 'riscv' into small_progbuf 
Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
 2017-11-01 13:38:17 -07:00
Tim Newsome db754536e8 Support 64-bit FPRs on RV32. 
Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.

I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.

Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.

This change improves Issue #110 but there's more work to be done.

Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
 2017-10-27 13:15:22 -07:00
Tim Newsome 1acb128290 Remove unused variables. 
Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
 2017-10-25 13:37:56 -07:00
Tim Newsome 23bd6d08c9 Remove more unused functionality. 
Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
 2017-10-24 15:11:33 -07:00
Tim Newsome dbecbfee99 Add a fence after memory writes. 
Change-Id: I5137479b685f735aa573cec5d40170016c40f597
 2017-10-24 12:15:25 -07:00
Tim Newsome 59a0340261 Remove more unused code. 
Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
 2017-10-24 11:38:39 -07:00
Tim Newsome 8432b7cf3d Remove more unused code. 
Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
 2017-10-24 11:34:48 -07:00
Tim Newsome 3ba6d46fc2 Remove unused functionality. 
Change-Id: Ic70cebd62bbd04f7ae5566504fbb279a11de57f0
 2017-10-23 14:45:58 -07:00
Tim Newsome 5425c871c9 Properly fix memory read when encountering busy. 
Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
 2017-10-23 14:13:46 -07:00
Tim Newsome a3a137062d Pay attention to impebreak. 
This required updating debug_defines.h, which caused a few other small
cleanups as well.

Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
 2017-10-18 14:21:23 -07:00
Tim Newsome 85bfab36ad Remove unused functionality. 
Change-Id: I0c1464e2e6aa12d0cb1025ed0a7c1c483e7403b7
 2017-10-18 12:47:07 -07:00
Tim Newsome 5d3f5c35d2 Still restore registers if an access failed. 
Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
 2017-10-18 12:32:41 -07:00
Tim Newsome 7edd9b1786 Fix FPR access. 
Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
 2017-10-18 11:47:15 -07:00
Tim Newsome a0623b2fa8 Don't crash when encountering RV64. 
Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
 2017-10-17 11:58:51 -07:00
Tim Newsome 65be0776d8 Memory read/write works if the core can keep up. 
Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
 2017-10-17 11:52:07 -07:00
Tim Newsome fbe2980eb7 MemTest64 passes. 
Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
 2017-10-17 11:15:51 -07:00
Tim Newsome d94b38279a Memtest{16,32} pass. 
Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
 2017-10-16 21:08:59 -07:00
Tim Newsome 7ec7bc32fe At least some memory writes work. 
Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
 2017-10-13 12:50:02 -07:00
Tim Newsome e7bb815e87 Register read/write might be working. 
Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
 2017-10-12 14:38:52 -07:00
Tim Newsome 94e8250713 WIP; doesn't work. 
Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
 2017-10-12 11:45:52 -07:00
Tim Newsome 77802af655 Remove duplicate progbuf size variable. 
Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
 2017-10-10 16:27:51 -07:00
Tim Newsome 24658db50e Fix compile warnings. 
Partly fixes #124.

Change-Id: I3a7fd65c643e40b142709806cb9fb4cc62bb955f
 2017-10-04 16:02:30 -07:00
Tim Newsome abe7eba25a Merge pull request #118 from riscv/priv 
Fix priv access
 2017-10-04 12:52:21 -07:00
Tim Newsome a3c26250bf Merge pull request #116 from riscv/multigdb 
Fix trigger code to work with multi-gdb mode instead of RTOS mode
 2017-10-03 11:53:58 -07:00
Liviu Ionescu f9f303923e target/riscv/asm.h: use tab for indentation 2017-10-03 00:36:22 +03:00
Liviu Ionescu f5a69e547f target/riscv/program.c: fix clang warning 
- I'm not sure I understand the logic behind the original statement,
but on macOS it fails to compile.
 2017-10-03 00:23:14 +03:00
Liviu Ionescu 728a617bd4 target/riscv: Silence -Werror=return-type 
- clang compains about the functions not returning a value
 2017-10-03 00:17:57 +03:00
Tim Newsome e64bb8c44a Fix priv access on 0.13. 2017-09-30 14:15:37 -07:00
Tim Newsome 6795270a8e Make priv readable in 0.11. 2017-09-30 13:31:57 -07:00
Tim Newsome 1083352576 Share register numbers between 0.11 and 0.13. 2017-09-30 13:13:03 -07:00
Tim Newsome 51f73a6769 Fix triggers for multi-gdb mode. 2017-09-26 15:40:49 -07:00
Tim Newsome 744894e965 Better debug messages. 2017-09-26 15:40:41 -07:00
Tim Newsome f0195868d3 Fall back on ndmreset if hartreset is unsupported. 2017-09-21 14:53:12 -07:00
Tim Newsome fe36097ff8 Fix reset for multicore. 2017-09-21 12:42:40 -07:00
Tim Newsome 848fe0ffcf Cleaning up single-hart reset. 2017-09-19 17:41:52 -07:00
Tim Newsome 4e701669b7 Merge pull request #113 from riscv/macos_build 
Add clang build
 2017-09-19 14:11:10 -07:00
Tim Newsome 60354cbea2 clang fix, don't allow unaligned uint64_t pointers 2017-09-18 14:56:46 -07:00
Tim Newsome ed9a04bde9 Remove unnecessary abs(). 2017-09-18 14:35:47 -07:00
Tim Newsome 0abd94b50c Make constants unsigned for clang. 2017-09-18 14:23:59 -07:00
Tim Newsome 604dfa0dcc Try to fix some clang warnings. 2017-09-18 14:03:33 -07:00
Tim Newsome 157a67a98a Be more clear in multi-core systems without -rtos 
Don't print out there's a hart with XLEN of 0.
 2017-09-18 11:29:14 -07:00
Tim Newsome ce20be3d78 Add support for F extension. 2017-09-14 16:23:47 -07:00
Tim Newsome f9b2549e20 Tell user how to increase timeout. 2017-09-11 12:11:24 -07:00
Tim Newsome a6ec1a0e68 Add timeout to another infinite loop. 2017-09-11 11:35:47 -07:00
Tim Newsome 12aca4ab7e Merge branch 'riscv' into keepalive 2017-08-30 12:09:51 -07:00
Tim Newsome 3c25b9a0c4 Merge pull request #105 from riscv/memread 
memory read is now completely stable even on intermittently slow targets
 2017-08-29 17:33:51 -07:00
Tim Newsome 6721988ce3 Ensure read_memory() only reads each address once. 
Previously it might read an address multiple times if an abstract
command took longer to execute than expected.

The new implementations reads from the target how far it has gotten
along reading memory, and resumes from there if cmderr=busy.

This ended up being a bigger change than I envisioned, but in the end it
deleted more lines than it added, so I'm happy. :-)
 2017-08-29 17:25:04 -07:00
Tim Newsome 2efc415db4 Finally nailed memory read on slow targets 
The downloaded program now post-increments, and there's no longer an
attempt to read the current address from the target. This made it easier
to fix the problem where at the start of the loop the current address
was already read (in regular entry) or has not yet been read (when the
first round through the loop encountered busy more than once, or busy
was encountered at least once later on).
 2017-08-28 11:17:55 -07:00
Tim Newsome 5f53655e65 Fix off-by-one error. 2017-08-26 18:25:10 -07:00
Tim Newsome eef9442aa7 Remove redundant code. 2017-08-26 17:50:05 -07:00
Tim Newsome 5bdee8bc66 Fix off-by-3 error on 64-bit targets. 
This caused everything to fall apart when debugging slow 64-bit targets.
 2017-08-26 17:49:13 -07:00
Tim Newsome 8bcec87cc1 Remove unnecessary \n 2017-08-26 16:53:00 -07:00
Tim Newsome 92ef328161 Don't reset DMI when an abstract command is busy. 2017-08-25 18:14:08 -07:00
Tim Newsome a9bcc48064 Remove unnecessary newlines. 2017-08-25 18:14:08 -07:00
Palmer Dabbelt 322669ca98 Merge pull request #95 from riscv/memread 
Fix block memory reads on slow targets.
 2017-08-25 16:57:07 -07:00