f341db9f72
WIP xml register for 0.11.
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On HiFive1, FPRs show up with no name, and misa is 0x1105 instead of
0x40001105.
Change-Id: I4ee223c905ad7d860147014e7b6394668658c6ea
2017-12-19 10:41:48 -08:00
8926e66d3a
Hide unknown registers, which probably don't exist
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Change-Id: Iffa8fa5ff4b0a01abd30fa302b7087e2011337bf
2017-12-19 10:41:48 -08:00
26a54452d2
Fix register names.
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Use the ABI ones for every register that we have one for.
Change-Id: I2a993abff416d2652dbe026b3fb498e144a5006f
2017-12-19 10:41:48 -08:00
7c989698a1
WIP better CSR names, and include only existing
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Change-Id: I1a234ee07c417ba56da10a61fc2bdbdcc60490a8
2017-12-19 10:41:48 -08:00
a5cb0b2270
WIP. Hide FPRs if the hart doesn't support F/D.
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Change-Id: I988c0c36f2de8157d76874a697b3c054773b787d
2017-12-19 10:41:48 -08:00
e648856a41
`make all` debug tests now pass.
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Also properly support (I think) D extension on RV32.
Change-Id: I2f0162d36e4c18c251f99b6943403cef30d17d29
2017-12-19 10:41:48 -08:00
c421fefdcb
Checkpoint that seems to work.
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Change-Id: I9599aacc256f6340795097732b6f8e8869c2099f
2017-12-19 10:41:48 -08:00
6aff46adcc
Fix cut and paste bug.
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Now reading 64-bit FPRs on 32-bit harts using scratch memory might work.
Change-Id: Ie8c0fc689386c6e724ecab5e8c855e725fa8dd97
2017-12-14 13:51:13 -08:00
0a65a6527d
Fix build.
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Change-Id: I4e3a36fac77fefa271ae9facbaa990fa330501ae
2017-12-11 12:58:20 -08:00
52cdf286ca
Add missing return.
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Change-Id: Ida32482903cdfd8eeb043088e84bb1f4f5ac673c
2017-11-16 15:58:08 -08:00
e28abf7c9e
Merge branch 'riscv' into small_progbuf
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Change-Id: I1d48cb1f8448ebbf98c8bb369928d1e7a7a78c75
2017-11-01 13:38:17 -07:00
db754536e8
Support 64-bit FPRs on RV32.
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Because there is no instruction that moves just half of a 64-bit FPR
to/from a GPR, we need to use scratch memory for this operation. This
code can theoretically use:
1. DMI_DATA, if it is memory mapped in the target.
2. DMI_PROGBUF, if it is writable in the target.
3. A user-configured address.
I have only tested this code very lightly. One reason is that gdb thinks
that on RV32 harts every register is 32 bits wide. Another is that this
is mostly proof-of-concept to satisfy the small program buffer code
review, which I don't want to drag out forever.
Existing tests don't realize that floating support was broken with
RV32D, and don't realize that it still doesn't work because of the gdb
problem mentioned above.
This change improves Issue #110 but there's more work to be done.
Change-Id: I99b8a36e5fea26f1d9e16e36cf99adc7be26b944
2017-10-27 13:15:22 -07:00
1acb128290
Remove unused variables.
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Change-Id: I678d0a65c22792895375dc6916381f81af8f83e4
2017-10-25 13:37:56 -07:00
23bd6d08c9
Remove more unused functionality.
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Change-Id: I43283b9556c959f891a587fb39bdd1ab9206e8af
2017-10-24 15:11:33 -07:00
dbecbfee99
Add a fence after memory writes.
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Change-Id: I5137479b685f735aa573cec5d40170016c40f597
2017-10-24 12:15:25 -07:00
59a0340261
Remove more unused code.
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Change-Id: I962660f58d948f85df6e073065e15e5d8f4a02b6
2017-10-24 11:38:39 -07:00
8432b7cf3d
Remove more unused code.
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Change-Id: Id91237c163d86e8f4d039503ca33b4ad7571ecd1
2017-10-24 11:34:48 -07:00
5425c871c9
Properly fix memory read when encountering busy.
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Change-Id: I377054495e860076edc2f38d1cc0f11c23f98d3b
2017-10-23 14:13:46 -07:00
a3a137062d
Pay attention to impebreak.
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This required updating debug_defines.h, which caused a few other small
cleanups as well.
Change-Id: I3c2cb418d7eff3093d7664c5563b2af5e8b530eb
2017-10-18 14:21:23 -07:00
5d3f5c35d2
Still restore registers if an access failed.
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Change-Id: I11571f0926f69a34f95b4929f633fdecd3a4e810
2017-10-18 12:32:41 -07:00
7edd9b1786
Fix FPR access.
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Change-Id: I1379de87904f1cf40b45d1a5490249e3ba90d7d0
2017-10-18 11:47:15 -07:00
a0623b2fa8
Don't crash when encountering RV64.
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Change-Id: Ie915ce830c3499919e4918ad443a5e225cf8c4d9
2017-10-17 11:58:51 -07:00
65be0776d8
Memory read/write works if the core can keep up.
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Change-Id: Ieca50ece266fbc9d2ff16a5cc2e6b4b926ad5e6f
2017-10-17 11:52:07 -07:00
fbe2980eb7
MemTest64 passes.
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Change-Id: I75996b71c3f31025c89ef596a08e01d191405336
2017-10-17 11:15:51 -07:00
d94b38279a
Memtest{16,32} pass.
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Change-Id: I15c2a4fd2bb9a7b30762d07f3b3a74d2f477746b
2017-10-16 21:08:59 -07:00
7ec7bc32fe
At least some memory writes work.
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Change-Id: I6fcf261341f10ec34df01bb844744439d02471a8
2017-10-13 12:50:02 -07:00
e7bb815e87
Register read/write might be working.
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Change-Id: I6c51d6157dde56d8cd666b4d30ec7bbc7a4bef9f
2017-10-12 14:38:52 -07:00
94e8250713
WIP; doesn't work.
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Change-Id: Ia407e82ccbd2044ad61e0845d285dd5765154476
2017-10-12 11:45:52 -07:00
77802af655
Remove duplicate progbuf size variable.
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Change-Id: I662ff84d13ecfc7faae51406a4df57a3643116f0
2017-10-10 16:27:51 -07:00
abe7eba25a
Merge pull request #118 from riscv/priv
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Fix priv access
2017-10-04 12:52:21 -07:00
e64bb8c44a
Fix priv access on 0.13.
2017-09-30 14:15:37 -07:00
744894e965
Better debug messages.
2017-09-26 15:40:41 -07:00
f0195868d3
Fall back on ndmreset if hartreset is unsupported.
2017-09-21 14:53:12 -07:00
fe36097ff8
Fix reset for multicore.
2017-09-21 12:42:40 -07:00
848fe0ffcf
Cleaning up single-hart reset.
2017-09-19 17:41:52 -07:00
4e701669b7
Merge pull request #113 from riscv/macos_build
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Add clang build
2017-09-19 14:11:10 -07:00
0abd94b50c
Make constants unsigned for clang.
2017-09-18 14:23:59 -07:00
604dfa0dcc
Try to fix some clang warnings.
2017-09-18 14:03:33 -07:00
157a67a98a
Be more clear in multi-core systems without -rtos
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Don't print out there's a hart with XLEN of 0.
2017-09-18 11:29:14 -07:00
ce20be3d78
Add support for F extension.
2017-09-14 16:23:47 -07:00
f9b2549e20
Tell user how to increase timeout.
2017-09-11 12:11:24 -07:00
a6ec1a0e68
Add timeout to another infinite loop.
2017-09-11 11:35:47 -07:00
6721988ce3
Ensure read_memory() only reads each address once.
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Previously it might read an address multiple times if an abstract
command took longer to execute than expected.
The new implementations reads from the target how far it has gotten
along reading memory, and resumes from there if cmderr=busy.
This ended up being a bigger change than I envisioned, but in the end it
deleted more lines than it added, so I'm happy. :-)
2017-08-29 17:25:04 -07:00
2efc415db4
Finally nailed memory read on slow targets
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The downloaded program now post-increments, and there's no longer an
attempt to read the current address from the target. This made it easier
to fix the problem where at the start of the loop the current address
was already read (in regular entry) or has not yet been read (when the
first round through the loop encountered busy more than once, or busy
was encountered at least once later on).
2017-08-28 11:17:55 -07:00
5f53655e65
Fix off-by-one error.
2017-08-26 18:25:10 -07:00
eef9442aa7
Remove redundant code.
2017-08-26 17:50:05 -07:00
5bdee8bc66
Fix off-by-3 error on 64-bit targets.
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This caused everything to fall apart when debugging slow 64-bit targets.
2017-08-26 17:49:13 -07:00
92ef328161
Don't reset DMI when an abstract command is busy.
2017-08-25 18:14:08 -07:00
a9bcc48064
Remove unnecessary newlines.
2017-08-25 18:14:08 -07:00
322669ca98
Merge pull request #95 from riscv/memread
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Fix block memory reads on slow targets.
2017-08-25 16:57:07 -07:00
4d0e88d887
Merge pull request #100 from riscv/riscv_timeout_commands
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riscv: Add commands for setting timeouts
2017-08-25 09:49:15 -07:00
879c274cb9
riscv: Add commands for setting timeouts
2017-08-15 15:59:40 -07:00
0ff4103a26
Reset address if target was busy during bust write
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Improve Issue #98 .
DebugCompareSections is still failing for me (with an instrumented
sometimes-slow spike), but MemTestBlock now passes reliably.
2017-08-15 15:47:35 -07:00
5c39079a62
Remove some unnecessary casts.
2017-08-15 14:29:24 -07:00
0d74c8689d
Fix block memory reads on slow targets.
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The interesting new code concerns ignore_prev_addr and
this_is_last_read.
Additionally, I tweaked some debug output, and optimized
riscv_batch_run() when the batch is empty.
2017-08-14 15:02:19 -07:00
2706df0ec3
Fix a corner case in block memory read.
2017-08-13 14:14:23 -07:00
3109da7dfd
Force actual read from prog buffer for the last transaction in read_memory()
2017-08-12 14:51:12 -07:00
e676d3dae6
Fixed off-by-one error in previous commit
2017-08-11 17:46:35 -07:00
39b01259fa
fixed memory leak introduced by previous commit
2017-08-10 16:37:50 -07:00
b5692585de
Fix reads beyond requested memory range
2017-08-10 14:27:11 -07:00
efcfcf555f
Fix assertion failure when reading from address 0.
2017-08-09 12:42:17 -07:00
b032eb1bcc
Use a wall clock timeout to complete reset.
2017-07-16 11:48:12 -07:00
f0f1df1061
Fix infinite loop in reset.
2017-07-14 12:50:11 -07:00
d60dbd60e8
Share trigger code between 0.11 and 0.13 code.
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The actual implementation of triggers didn't change between those two
versions, so there's no need to duplicate the code.
In the process, I also fixed a minor multicore bug where tselect didn't
always get written on all harts.
2017-07-12 19:54:40 -07:00
2deb02695e
Forgot to commit this follow up to PR #79
2017-07-12 17:51:38 -07:00
09bf86e31a
Keep around cmderr for callers to inspect.
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Use this to only change abstract register access behavior when cmderr
explicitly says the requested operation is unsupported.
2017-07-12 14:36:09 -07:00
856f70fe44
Try abstract register writes as well.
2017-07-12 14:13:31 -07:00
f37e93bbc0
Try using abstract commands to read registers
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This is the only way the spec guarantees that GPRs are accessible, and
depending on the implementation this might be the only way that CSRs are
accessible.
Also changed the debug code that parses out DMI fields to be simpler to
maintain (albeit a little slower).
riscv013_execute_debug_buffer() now automatically clears cmderr if the
command fails. That feels like the right behavior. (It does return the
error to its caller.)
2017-07-12 14:13:31 -07:00
4072fa493b
Disable debugger-set triggers on connect
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When first connecting to a target, have the debugger disable any
hardware triggers that are set by a previously connected debugger.
The 0.11 code already did this, but 0.13 did not.
To achieve this I decided to share the code to enumerate triggers
between 0.11 and 0.13, which required me to implement get_register() and
set_register() for 0.11, which made the whole change a lot larger than
you might have guessed.
Hopefully this sets us up to in the future share the code to set/remove
triggers as well.
2017-07-10 10:26:24 -07:00
31e5b53a46
Merge pull request #74 from riscv/build32
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Fix 32-bit build errors.
2017-07-06 13:41:47 -07:00
3cff4213a4
Merge pull request #69 from riscv/multi-gdb
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Fix the multi-GDB mode bugs
2017-07-03 13:18:06 -07:00
450307b66f
Fix 32-bit build errors.
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I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71 .
2017-07-03 12:17:07 -07:00
f18fd83ac7
Fix trigger set/clear bug.
2017-07-03 11:52:35 -07:00
99a3673507
Fix comment about saving the temporary register in examine procedure.
2017-07-01 15:09:23 +03:00
7d451e00f5
Restore value of temporary register (s0) in examine OpenOCD procedure in case of core can not execute 64 bit instruction.
2017-06-30 19:15:58 +03:00
d77c4a953c
Don't set breakpoints on disabled harts
2017-06-21 12:25:20 -07:00
4bdb042224
Allow memory writes to proceed on all harts
2017-06-21 12:25:19 -07:00
a277416a39
Refactor examine, to avoid some assertions
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Now that we're supporting non-RTOS multi-hart mode there's some more
assertions that you're running on the right hart. Those assertions
aren't sane very early in examine, so I avoid them.
2017-06-21 12:25:19 -07:00
788908fcf0
Factor out checking if harts should be used
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Rather than having a bunch of "if rtos" stuff, I now just check "if
hart_enabled". This makes some code paths cleaner, all of which were
buggy in the non-RTOS multi-hart mode.
2017-06-21 10:09:16 -07:00
9f4cac5a38
Set current_hartid from coreid
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This avoids a bunch of RTOS special cases.
2017-06-20 17:19:05 -07:00
9cd98058a0
Set hardware triggers on all harts.
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Right now we're using "threads" to represent harts. gdb/OpenOCD assume
there's only one set of hardware breakpoints among all threads. Make it
so.
2017-06-20 13:10:35 -07:00
ccdd26e3ef
Comment curious code.
2017-06-20 11:32:42 -07:00
927f9d8873
Update list of "threads" when harts are discovered.
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This ensures that "info threads" is accurate as soon as gdb connects.
Also print out number of triggers that is discovered in examine().
2017-06-20 11:32:42 -07:00
4d264b3579
Put early DEBUG notice of XLEN back.
2017-06-19 08:46:02 -07:00
6082f35a55
Update debug_defines. Clarify debug output.
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Update debug_defines from the spec, commit 920ec9a690.
Decode dmstatus scans in the debug output.
2017-06-16 14:02:25 -07:00
fd81f7fcac
Fix comment.
2017-06-16 14:02:25 -07:00
851849a295
Tell the user about detected harts.
2017-06-16 14:02:25 -07:00
ac2da40f74
Fix indentation to match OpenOCD style.
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This change is just in the whitespace. There are no code changes.
See http://openocd.org/doc-release/doxygen/stylec.html
2017-06-15 12:44:50 -07:00
363a0a2bf2
Merge pull request #64 from riscv/release-fixes
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Two fixes from the release branch
2017-06-15 12:43:46 -07:00
50a223ef9a
Fix print statements to work with 64-bit addresses
2017-06-15 12:24:37 -07:00
099a3020d2
Clear abstract errors from register_read_direct
2017-06-15 12:16:24 -07:00
64af052911
Fix the build.
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Main change is to make riscv_addr_t be unsigned. The rest is mechanical
fixing of types, print statements, and a few signed/unsigned compares.
Smoketest indicates everything is working more or less as before.
2017-06-13 12:33:01 -07:00
6be600318c
Fix dmi_read() indentation; remove \n in LOG_ERROR
2017-06-08 12:31:08 -07:00
c3b344d1c0
riscv: Move the initialization of the field inside the structure for consistency
2017-06-07 21:06:33 -07:00
459b39ec67
riscv: v13 -- dmi_write must still check for the OP result
2017-06-07 21:06:33 -07:00
c431c0eb25
Check for abstractcs.busy, not just CMDERR_BUSY
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This fixes a race condition when reading/writing memory.
2017-05-15 17:40:28 -07:00
a8cf04b839
Go back to 32-word read/write buffers
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The larger buffers are really slow on Spike.
2017-05-15 16:57:25 -07:00
e31761df64
Don't re-read registers after they're written
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This was just a sanity check.
2017-05-15 16:57:08 -07:00
9d308db2bc
Print out the actual CSR that's read
2017-05-15 16:56:50 -07:00
8252b9d36c
Build fixes
2017-05-15 13:39:58 -07:00
Tim Newsome
Palmer Dabbelt
Megan Wachs
Gleb Gagarin
Dmitry Ryzhov