Mostly addresses #207.
Also changed dmi_read() to return an error, and fixed all the call sites
to propagate that error if possible.
Change-Id: Ie6fd1f9e7eb46ff92cdb5021a7311ea7334904f1
Instead of asserting, return error when an abstract register access
fails on running target.
Fixes#201
Change-Id: I1ab3b31b0a4babf83c44f95ee2eeca92ef906d2f
It confuses users of IDEs like Eclipse, which request to read registers
that don't exist on the target.
Fixes#176
Change-Id: Ie2504140bfc70eba0d88fd763aacd87895aa20ff
When authdata_write sets the authenticated bit, examine() every OpenOCD
target that is connected to the DM that we were authenticated to.
Change-Id: I542a1e141e2bd23d085e507069a6767e66a196cd
They can be used to authenticate to a Debug Module.
There's a bit of a chicken and egg problem here, because the RISCV
commands aren't available until the target is initialized, but
initialization involves examine(), which can't interact with the target
until authentication has happened. So to use this you run `init`, which
will print out an error, and then run the `riscv authdata_read` and
`riscv authdata_write` commands. When authdata_write() notices that the
authenticated bit went high, it will call examine() again.
Example usage (very simple challenge-response protocol):
```
init
set challenge [ocd_riscv authdata_read]
riscv authdata_write [expr $challenge + 1]
reset halt
```
Change-Id: Id9ead00a7eca111e5ec879c4af4586c30af51f4d
... by disabling all triggers, single stepping, enabling them, and then
resuming as usual. Without this change, you'd just be stuck on an
address trigger and would have to manually disable it.
Change-Id: I5834984671baa6b64f72e533c4aa94555c64617e
Fixed abstract register access for registers that aren't XLEN wide.
Avoided excessive errors cases where we attempted to execute a fence but
failed.
Don't mark all the CSRs as caller-save. gdb was saving/restoring
dscratch, which broke function calls as a side effect. dscratch is
accessible for people who really know what they're doing, but gdb should
never quietly access it. The same is probably true for other CSRs.
Change-Id: I7bcdbbcb7e3c22ad92cbc205bf537c1fe548b160
It's not tested because spike never reports any busy errors since every
access happens instantaneously.
Change-Id: If43ea233a99f98cd419701dc98f0f4a62aa866eb
As part of this I improved the memory read/write fatal error handling a
bit. Now at least we try to leave autoexec turned off, and will even
restore the temp registers if the situation isn't too hosed for that.
Partly addresses Issue #142
Change-Id: I79fe3f862f11c6d20441f39162423357e73a40c1
Tim Newsome
Kaspar Schleiser
Gleb Gagarin