Currently the cmd 'cortex_m3 reset_config' will overide the default
target's 'reset_config'.
Chnage the behaviour to use the target 'reset_config' if configured and
fallback if not.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
it's a lie that is somewhere in the vicinity of the
truth. Certainly 64MHz confuses gprof and produces
zero output and no error messages.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
If the CPU crashed at some point, poll will discover this.
Previously the poll fn would clear the error and print a warning,
rather than propagating the error.
The new behavior is to report the error back up, but still
clear the error.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Implement autodetection of debug base. Also, implement a function solving
various hardware quirks (like iMX51 ROM Table location bug).
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This patch implements "dap_lookup_cs_component()", which allows to lookup CS
component by it's identification.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This patch adds function called "dap_detect_debug_base()", which should be
called to get location of the ROM Table. By walking ROM Table, it's possible to
discover the location of DAP.
Sadly, some CPUs misreport this value, therefore I had to introduce an fixup
table, which will be used in case such CPU is detected.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
So far most of the people have been using existing ARM966E in the
place of ARM946E, because they have practically the same scan chains.
However, ARM946E has caches, which further complicates JATG handling
via scan-chain. this was preventing single-stepping for ARM946E when
SW breakpoints are used.
This patch thus introduces :
1) Correct cache handling on memory write
2) Possibility to flush whole cache and turn it off during debug, or
just to flush affected lines (faster and better)
3) Correct SW breakpoint handling and correct single-stepping
4) Corrects the bug on CP15 read and write, so CP15 values
are now correctly R/W
Collect variable definitions.
Report syntax error to command dispatcher.
Propagate error when unable to open file.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
short story: if the JTAG clock is too high, then the
behavior will be flaky and kludging the code may
seem to make things beter, but really it's just a red
herring.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
A while back I sent in a patch that adds support for watchpoint lengths greater
than four on xscale. It's been working well, until the other day, when it
caused an unexpected debug exception. Looking into this I realized there is a
case where it breaks: when the length arg is greater than the base address.
This is a consequence of the way the hardware works. Don't see a work-around,
so I added code to xscale_add_watchpoint() to check for and disallow this
combination.
Some more detail... xscale watchpoint hardware does not support a length
directly. Instead, a mask value can be specified (not to be confused with the
optional mask arg to the wp command, which xscale does not support). Any bits
set in the mask are ignored when the watchpoint hardware compares the access
address to the watchpoint address. So as long as the length is a power of two,
setting the mask to length-1 effectively specifies the length. Or so I thought,
until I realized that if the length exceeds the base address, *all* bits of the
base address are ignored by the comaparator, and the watchpoint range
effectively becomes 0 .. length.
Questions, comments, criticisms gratefully received.
Thanks,
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Hi everyone,
Added more LOG_ERROR messsages to watchpoint and breakpoint code, given that the
infrastructure no longer interprets returned error codes. Also changed
existing LOG_INFO and LOG_WARNING to LOG_ERROR for cases where an error is
returned.
Note that the check of the target state is superflous, since the infrastruture
code currently checks this before calling target code. Is this being
reconsidered as well? Also, should we stop returning anything other than
ERROR_OK and ERROR_FAIL?
Comments gratefully received.
Thanks,
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
do not try to interpret "retval" into a string, just
amend a bit about the context of the already reported
error.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
Version 2 of this patch. Code added to breakpoints.c was removed from previous
patch, and item 3 added, per discussion with Øyvind regarding error reporting.
Item 4 added, which I just noticed.
I tried to use a software breakpoint in thumb code on the xscale for the first
time recently, and was surprised to find that it didn't work. The result was
this patch, which does four things:
1): fix trivial cut-n-paste error that caused thumb breakpoints to not work
2): call xscale_set_breakpoint() from xscale_add_breakpoint()
3): log error on data abort in xscale_write_memory()
4): fixed incorrect error code returned by xscale_set_breakpoint() when no
breakpoint register is available; added comment
Item 2 not only makes the xscale breakpoint code consistent with other targets,
but also alerts the user immediately if an error occurs when writing the
breakpoint instruction to target memory (previously, xscale_set_breakpoint() was
not called until execution resumed). Also, calling xscale_breakpoint_set() as
part of the call chain starting with handle_bp_command() and propagating the
return status back up the chain avoids the situation where OpenOCD "thinks" the
breakpoint is set when in reality an error ocurred.
Item 3 provides a helpful message for a common reason for failure to set sw
breakpoint.
This was thoroughly tested, mindful of the fact that breakpoint management is
somewhat dicey during single-stepping.
Comments and criticisms of course gratefully received.
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
I figured since I was poking around in the breakpoint code on other arches, I'd
add this change to those arches that don't do it already. This patch propagates
the return code of <arch>_set_breakpoint() up the call stack. This ensures that
the higher layer breakpoint infrastructure is aware that an error ocurred, in
which case the breakpoint is not recorded.
Normally I wouldn't touch code that I can't test, but the code is very
uniform across architectures, and the change is rather benign, so I figured
after careful inspection that it is safe. If the maintainers or others think
this is imprudent, the patch can be dropped.
Also changed the error code to something more appropriate in two cases where
hardware resources are unavailable.
Comments and criticisms of course gratefully received.
Mike
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Hi everyone,
This simple patch fixes a problem I noticed on the xscale where incorrect values
are sometimes reported by the reg command. The problem can occur when
requesting the value of registers in the xscale-specific register cache. With a
couple of exceptions, none of the registers in the xscale register cache are
automatically retrieved on debug entry. This is probably fine, as they are
unlikely to be needed on a regular basis during a typical debug session, and
they can be retrieved when explicitly requested by name using the reg command.
The problem is that once this is done, the register remains marked as valid for
the remainder of the OpenOCD session, and the reg command will henceforth always
report the same value because it is obtained from the cache and is never again
retrieved from the debug handler on the target.
The fix is to mark all registers in the xscale register cache as invalid on
debug entry (before the two exceptions are retrieved), thus forcing retrieval
(when requested) from the target across resumptions in execution, and avoiding
the reporting of stale values.
Small addition change by Øyvind: change 'i' to unsigned to fix compiler
warning for xscale_debug_entry() fn.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This new cmd adds the ability to choose the Cortex-M3
reset method used.
It defaults to using SRST for reset if available otherwise
it falls back to using NVIC VECTRESET. This is known to work
on all cores.
Move any luminary specific reset handling to the stellaris cfg file.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
committed so as to ease cooperation and to let it be improved
over time.
So far it supports:
- halt/resume
- registers inspection
- memory inspection/modification
I'm still getting up to speed with OpenOCD internals and AVR32 so code is a little
bit messy and I'd appreciate any feedback.
ocd_ prefix is used internally in OpenOCD as a kludge more
or less to deal with the two kinds of commands that OpenOCD
has.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
if polling is off, then "reset run + halt" would fail
since halt incorrectly assumed the target was in the
reset state as it is the internal poll implementation
that moves the sw tracking of the target state out
of the reset state.
To reproduce:
> reset run; halt
JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
back-off algorithm for polling. Double polling
interval up to 5000ms when it fails.
when polling succeeds, reset backoff.
This avoids flooding logs(as much) when working
with conditions where the target polling will fail.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
It is useful to know that the printed errors are *all* the
errors there were.
Added missing error handling(found by inspection).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
As the mips32 uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm codebase.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
As the armv7m uses instruction breakpoints for algorithms we do not really
need to check the pc on exit.
This now matches the behaviour of the arm4_5 codebase.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Update the arm_checksum_memory and arm_blank_check_memory
algorithms to use a breakpoint instruction on v5 arch.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Use addition for offsetting, not masking. Shorten some lines.
Make "component_start" print-only (unused otherwise; don't save).
Still doesn't resolve the issue where multiple components
are wrongly displaying as NVICs on some Cortex-M3 parts because
many PIDs appear to be zeroes ... maybe adapter related??
Signed-off-by: David Brownell <db@helium.(none)>
Mask the upper bits after 32-bit reads.
Alsoo revert the ugly changes to use PRIx32; just cast to unsized
integers when printing (two chars not eight).
Signed-off-by: David Brownell <db@helium.(none)>
This reverts the incorrect change made to the arm9 cmd group in commit
d1eca9a74c.
The code now matches the docs and the release notes.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
The code did not transfer the last word in no-ack transfers.
The strange thing is that this did not lead to any
observable errors.
This gaffe was introduced in commit 1f5883ea56
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Review allocation of error numbers in openocd
to avoid overlap.
Put brackets around negative numbers to avoid
issues during macro expansion.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Memory read/writes to virtual memory, requires that the CPU is
halted.
Use 'phys' option to write to memory while target is running.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
when locking the debug access fails on the first try, it's a
bit noisy, so print out message that it succeeded on second try.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Add "static" qualifier to private functions.
Move duplicated global declarations from "target/avrt.c"
and "nor/avrf.c" to "target/avrt.h".
Remove unused declarations form "nor/avrf.c".
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
normal code should not call jtag_get_error(), but rather check
the return code from jtag_execute_queue().
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
failure to write to memory was not propagated.
This is an interesting case of broken error handling:
with exceptions we wouldn't have had this at all,
and I also wonder if there is a GCC option to warn
about these kinds of potential bugs.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Parameter "type" of function armv4_5_mmu_translate_va()
is now not used.
Remove the parameter and the "enum" listing its values.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Function armv4_5_mmu_translate_va() now properly signals
errors in the return value.
Remove former error handling by setting variable "type" to
value "-1".
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Function arm920t_write_memory() default return value
should be ERROR_OK.
All cases of local errors are handled immediately and
not further propagated.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Commit 0538081246
introduces a compile time warning:
arm920t.c: In function ‘arm920t_write_memory’:
arm920t.c:567: warning: ‘retval’ may be used uninitialized in this function
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
ETM analyze produced no output when the trace buffer was empty.
This patch provides users with a clue.
Signed-off-by: Jon Povey <jon.povey@racelogic.co.uk>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
We request a id register read at the end of ahbap_debugport_init
but we never actually run the queue. In some cases this causes a
segfault.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
This second half of the patch is proposed to clean up some GDB keep alive
issues on arm7_9 targets that start up with very slow clocks. If an attempt
is made to write to key registers on the processor with a slow jtag speed,
GDB timeout warnings appear on the console (at least mine) when "reset halt"
or "reset init" commands are issued from the gdb client:
*** BEFORE PATCH ***
(gdb) monitor reset init
fast memory access is disabled
2 kHz
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1026). Workaround: increase "set remotetimeout" in GDB
JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (mfg: 0x01f, part:
0x7926, ver: 0x0)
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1027). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1006). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1006). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1006). Workaround: increase "set remotetimeout" in GDB
keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not
sent! (1004). Workaround: increase "set remotetimeout" in GDB
RCLK - adaptive
dcc downloads are enabled
fast memory access is enabled
NAND flash device 'NAND 256MiB 3,3V 8-bit' found
(gdb)
I added additional keep alive steps in areas that troubleshooting revealed
were causing problems. I only did this however for non-fast write memory
accesses. I don't think most people would be using fast memory accesses to
write to memory when the jtag and system clocks are slow anyway.
If you disagree with my feeling, think there is a more elegant way to handle
the problem, or think the patch will cause other unforeseen problems with
other targets, let me know. As you can see below, the patch does eliminate
the problem on my development station and I suspect that it will benefit
others.
*** AFTER PATCH ***
(gdb) monitor reset init
fast memory access is disabled
2 kHz
JTAG tap: at91sam9g20.cpu tap/device found: 0x0792603f (mfg: 0x01f, part:
0x7926, ver: 0x0)
target state: halted
target halted in ARM state due to breakpoint, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
MMU: disabled, D-Cache: disabled, I-Cache: disabled
RCLK - adaptive
dcc downloads are enabled
fast memory access is enabled
NAND flash device 'NAND 256MiB 3,3V 8-bit' found
(gdb)
Gary Carlson
Gary Carlson, MSEE
Principal Engineer
Carlson-Minot Inc.
Change download rate messages about kibibytes from "kb/s" to "KiB/s" units.
See: http://en.wikipedia.org/wiki/Data_rate_units
Signed-off-by: Jon Povey <jon.povey@racelogic.co.uk>
There are a million reasons why cached protection state might
be stale: power cycling of target, reset, code executing on
the target, etc.
The "flash protect_check" command is now gone. This is *always*
executed when running a "flash info".
As a bonus for more a more robust approach, lots of code could
be deleted.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Various commands, e.g. "arm mcr xxxx" would fail if invoked upon startup
since it there was no command context defined for the jim interpreter
in that case.
A Jim interpreter is now associated with a command context(telnet,
gdb server's) or the default global command context.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
target memory allocation can be implemented not to show
bogus error messages.
E.g. when trying a big allocation first and then a
smaller one if that fails.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This patch adds support for the length argument to the xscale implementation of
the wp command. Per discussion with David, the length argument specifies the
range of addresses over which a memory access should generate a debug exception.
This patch utilizes the "mask" feature of the xscale debug hardware to implement
the correct functionality of the length argument. Some limitations imposed by
the hardware are:
- The length must be a power of two, with a minumum of 4.
- Two data breakpoint registers are available, allowing for two watchpoints.
However, if the length of a watchpoint is greater than four, both registers
are used (the second for a mask value), limiting the number of watchpoints
to one.
This patch also removes a useless call to xscale_get_reg(dbcon) in
xscale_set_watchpoint() (value had already been read from the register cache,
and the same previously read value is then modified and written back).
I have been using and testing this patch for a couple days.
Questions, corrections, criticisms of course gratefully received.
This patch fixes the xscale_analyze_trace() function. This function was
defective for a trace collected in 'fill' mode (hiccups with repeated
instructions) and completely broken when buffer overflowed in 'wrap' mode. The
reason for the latter case is that the checkpoint registers were interpreted
incorrectly when two checkpoints are present in the trace (which will be true in
'wrap' mode once the buffer fills). In this case, checkpoint1 register will
contain the older entry, and checkpoint0 the newer. The original code assumed
the opposite. I eventually gave up trying to understand all the logic of the
function, and rewrote it. I think it's much cleaner and understandable now. I
have been using and testing this for a few weeks now. I'm confident it hasn't
regressed in any way.
Also added capability to handle (as best as possible) the case where an
instruction can not be read from the loaded trace image; e.g., partial image.
This was a 'TODO' comment in the original xscale_analyze_trace().
Outside of xcsale_analyze_trace(), these (related) changes were made:
- Remove pc_ok and current_pc elements from struct xscale_trace. These elements
and associated logic are useless clutter because the very first entry placed
in the trace buffer is always an indirect jump to the address at which
execution resumed. This type of trace entry includes the literal address in
the trace buffer, so the initial address of the trace is immediately
determined from the trace buffer contents and does not need to be recorded
when trace is enabled.
- Added num_checkpoints to struct xscale_trace_data, which is necessary in order
to correctly interpret the checkpoint register contents.
- In xscale_read_trace()
- Fix potential array out-of-bounds condition.
- Eliminate partial address entries when parsing trace (can occur in wrap mode).
- Count and record number of checkpoints in trace.
- Added small, inlined utility function xscale_display_instruction() to help
make the code more concise and clear.
TODO:
- Save processor state (arm or thumb) in struct xscale_trace when trace is
enabled so that trace can be analyzed correctly (currently assumes arm mode).
- Add element to struct xscale_trace that records (when trace is enabled)
whether vector table is relocated high (to 0xffff0000) or not, so that a
branch to an exception vector is traced correctly (curently assumes vectors
at 0x0).
+ virt2phys() can now convert virtual address to real
+ read_memory() and write_memory() are renamed to read_phys_memory()
and write_phys_memory()
+ new read_memory() and write_memory() try to resolve real address if
mmu is enambled than perform real address reading/writing
+ if address is bellow 0xc000000 than TTB0 is used for page table
dereference, if above - than TTB1. Linux style of user/kernel address
separation
+ if above fails (i.e address is unspecified) than mode is checked
whether it is Supervisor (than TTB1) or User (than TTB0)
- Software breakpoints doesn't work. You should invoke
"gdb_breakpoint_override hard" before you start debugging
+ cortex_a8_mmu(), cortex_a8_enable_mmu_caches(),
cortex_a8_disable_mmu_caches() are implemented
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
I'm not sure what caused this significant character to get deleted.
it may be related to intermittent Editor or terminal flakes I've
been seeing lately (sigh). This fix is trivial.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Fixing one bug can easily uncover another .... in this case,
making sure that we properly invalidate some cached NOR state when
resuming arbitrary target code turned up an issue when the code
wasn't quite arbitrary (and we couldn't know that, but some parts
of OpenOCD assumed the cache would not be invalidated.
Specifically: some flash drivers (like CFI) update that state in loops
with downloaded algorithms, thus invalidating the state as it's probed.
+ Add a new target state flag, to record whether the target is
running downloaded algorithm code.
+ Use that flag to add a special case: "trust" downloaded algorithms
not to corrupt that cached state, bypassing cache invalidation.
Also update some of the documentation to stipulate that this flavor of
trustworthiness is now *required* ... not just a fortuitous acident.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
For some reason there are *two* schemes for interposing logic into
the run_algorithm() code path... One is a standard procedural wapper
around the target method invocation.
the other (superfluous) one hacked the method table by splicing
a second procedural wrapper into the method table. Remove it:
* Rename its slightly-more-featureful wrapper so it becomes
the standard procedural wrapper, leaving its added logic
(where it should have been in the first place.
Also add a paranoia check, to report targets that don't
support algorithms without traversing a NULL pointer, and
tweak its code structure a bit so it's easier to modify.
* Get rid of the superfluous/conusing method table hacks.
This is a net simplification, making it simpler to analyse what's
going on, and then interpose logic . ... by ensuring there's only one
natural place for it to live.
------------
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Problem: halt at a breakpoint, enable trace buffer ('xscale trace_buffer enable
fill'), then resume. Wait for debug exception when trace buffer fills (if not
sooner due to another breakpoint, vector catch, etc). Instead, never halts.
When halted explicitly from OpenOCD and trace buffer dumped, it contains only
one entry; a branch to the address of the original breakpoint. If the above
steps are repeated, except that the breakpoint is removed before resuming, the
trace buffer fills and the debug exception is generated, as expected.
Cause: related to how a breakpoint is stepped over on resume. The breakpoint is
temporarily removed, and a hardware breakpoint is set on the next instruction
that will execute. xscale_debug_entry() is called when that breakpoint hits.
This function checks if the trace buffer is enabled, and if so reads the trace
buffer from the target and then disables the trace (unless multiple trace
buffers are specified by the user when trace is enabled). Thus you only trace
one instruction before it is disabled.
Solution: kind of a hack on top of a hack, but it's simple. Anything better
would involve some refactoring. This has been tested and trace now works as
intended, except that the very first instruction is not part of the trace when
resuming from a breakpoint.
TODO: still many issues with trace: doesn't work during single-stepping (trace
buffer is flushed each step), 'xscale analyze_trace' works only marginally for
a trace captured in 'fill' mode, and not at all for a trace captured in 'wrap'
mode.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
I don't know when "poll off" broke, but "poll off" didn't
stop background polling of target. The polling status flag
simply wasn't checked in the handle_target timer callback.
All target polling(including power/reset state) is now stopped
upon "poll off".
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This patch fixes xscale software breakpoints by cleaning the dcache and
invalidating the icache after the bkpt instruction is inserted or removed. The
icache operation is necessary in order to flush the fetch buffers, even if the
icache is disabled (see section 4.2.7 of the xscale core developer's manual).
The dcache is presumed to be enabled; no harm done if not. The dcache is also
invalidated after cleaning in order to safeguard against a future load of
invalid data, in the event that cache_clean_address points to memory that is
valid and in use.
Also corrected a confusing typo I noticed in a comment.
TODO (or not TODO...?): the xscale's 2K "mini dcache" is not cleaned. This
cache is not used unless the 'X' bit in the page table entry is set. This is a
proprietary xscale extension to the ARM architecture. If a target's OS or
executive makes use of this for memory regions holding code, the breakpoint
problem will persist. Flushing the mini dcache requires that 2K of valid
cacheable memory (mapped with 'X' bit set) be designated by the user for this
purpose. The debug handler that gets downloaded to the target will also need to
be extended.
the handling of caches, should be moved into the breakpoint
specific callbacks rather than being plonked into generic
memory write fn's.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
By a bit of code inspection it seems like all of these
instances of jtag_get_end_state() can be unambigously
replaced by constants.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Fix problem with the xscale icache and dcache commands. Both commands were
enabling or disabling the mmu, not the caches
I didn't look any further after my earlier patch fixed the trivial problem
with command argument parsing. Turns out the underlying code was broken.
The resolution is straightforward when you look at the arguments to
xscale_enable_mmu_caches() and xscale_disable_mmu_caches(). I finally
took a deeper look after dumping the cp15 control register (XSCALE_CTRL)
and seeing that the cache bits weren't changing, but the mmu bit was
(which caused all manner of grief, as you can imagine). This has been
tested and works OK now.
src/target/xscale.c | 17 +++++++++++------
1 files changed, 11 insertions(+), 6 deletions(-)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
So don't use the name "swjdp" for all DAPs; rename to
plain old "dap", which *is* always correct.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Not sure how the original "move code to adi_v5_swd.c" patch left
some code in the "arm_adi_v5.c" file, but a recent patch was only
a partial fix -- it didn't remove all the duplication.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
jtag_get/set_end_state() is now deprecated.
There were lots of places in the code where the end state was
unintentionally modified.
The big Q is whether there were any places where the intention
was to modify the end state. 0.5 is a long way off, so we'll
get a fair amount of testing.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
A fn was copied instead of moved to a new file. The linker
can discard exact copies of fn's without warning.
This is a C++'ism.
However on my Ubuntu 9.10 machine, it fails.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
The PIC32MX does not support the ejtag software reset - it is
optional in the ejtag spec.
We perform the equivalent using the microchip specific MTAP cmd's.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
The mips_m4k_assert_reset has now been restructured
so the variant ejtag_srst is not required anymore.
The ejtag software reset will be used if the target does not
have srst connected.
Remove ejtag_srst from docs.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Unused. If something should happen after context restore, then the
calling code can just do it afterwards.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Unclutter arm_adi_v5.c by moving most transport-specific code
to a transport-specific files adi_v5_{jtag,swd}.c ... it's not
a full cleanup, because of some issues which need to be addressed
as part of SWD support (along with implementing the DAP operations
on top of SWD transport):
- The mess where mem_ap_read_buf_u32() is currently coded to
know about JTAG scan chains, and thus needs rewriting before
it will work with SWD;
- Initialization is still JTAG-specific
Also move JTAG_{DP,ACK}_* constants from adi_v5.h to the JTAG
file; no other code should care about those values.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Fixes bug that prevented users from specifying a base address of
0x80000000 or higher in image commands (flash write_image, etm image,
xscale trace_image).
image.base_address is an offset from the start address contained in
the image file (if there is one), or from 0 (for binary files). As a
signed 32-bit int, it couldn't be greater than 0x7fffffff, which is a
problem when trying to write a binary file to flash above that
address. Changing it to a 64-bit long long keeps it as a signed
offset, but allows it to cover the entire 32-bit address space.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Simple patch that fixes the broken xscale icache and dcache commands.
This broke when the helper functions and macros were changed.
[ dbrownell@users.sourceforge.net: don't use strcasecmp ]
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add flash algorithm support for the PIC32MX.
Still a few things todo but this dramatically decreases
the programing time, eg. approx programming for 2.5k test file.
- without fastload: 60secs
- with fastload: 45secs
- with fastload and algorithm: 2secs.
Add new devices to supported list.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
In the code a single field was all that was ever used. Makes
jtag_add_ir_scan() simpler and leaves more complicated stuff
to jtag_add_plain_ir_scan().
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
jtag_add_dr/ir_scan() now takes the tap as the first
argument, rather than for each of the fields passed
in.
The code never exercised the path where there was
more than one tap being scanned, who knows if it even
worked.
This simplifies the implementation and reduces clutter
in the calling code.
use jtag_add_ir/dr_plain_scan() for more fancy situations.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Get rid of needless and undesirable code duplication for
all the DAP commands (resolving a FIXME) ... there's no
need for coreas to have private copies of that stuff.
Stick a pointer to the DAP in "struct arm", letting common
code get to it.
Also rename the "swjdp_info" symbol; just call it "dap".
This is an overall code shrink.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This partially corrects an inappropriate name choice (and its
associated FIXME).
There are still too many variables named "swjdp", bug little
current code actually relies on them referencing an SWJ-DP instead
of some other flavor of DAP. Only the two new dap_to{swd,jtag}()
calls could behave differently on an SWJ-DP instead of a SW-DP or
a JTAG-DP.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The NOR infrastructure caches some per-sector state, but
it's not used much ... because the cache is not trustworthy.
This patch addresses one part of that problem, by ensuring
that state cached by NOR drivers gets invalidated once we
resume the target -- since targets may then modify sectors.
Now if we see sector protection or erase status marked as
anything other than "unknown", we should be able to rely
on that as being accurate. (That is ... if we assume the
drivers initialize and update this state correctly.)
Another part of that problem is that the cached state isn't
much used (being unreliable, it would have been unsafe).
Those issues can be addressed in later patches.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make ADIv5 internals use the two new transport-neutral calls for reading
and writing DP registers; and do the same for external callers. Also,
bugfix some of their call sites to handle the fault returns, instead of
ignoring them.
Remove most of the JTAG-specific calls, using their code as the bodies
of the JTAG-specific implementation for the new methods.
NOTE that there's a remaining issue: mem_ap_read_buf_u32() makes calls
which are JTAG-specific. A later patch will need to remove those, so
JTAG-specific operations can be removed from this file, and so that SWD
support will be able to properly drop in as just a transport layer to the
ADIv5 infrastructure. (The way read results are posted may need some more
attention in the transport-neutrality interface.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make ADIv5 internals use the two new transport-neutral calls for reading
and writing DP registers. Also, bugfix some of their call sites to
handle the fault returns, instead of ignoring them.
Remove the old JTAG-specific calls, using their code as the bodies
of the JTAG-specific implementation for the new methods.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make ADIv5 use one of the new transport-neutral interfaces: call
dap_run(), not jtagdp_transaction_endcheck().
Also, make that old interface private; and bugfix some of its call
sites to handle the fault returns, instead of ignoring them.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
To support both JTAG and SWD, ADIv5 needs DAP operations which are
transport-neutral, instead being of JTAG-specific. This patch:
- Defines such a transport-neutral interface, abstracting access
to DP and AP registers through a conceptual queue of operations.
- Builds the first implementation of such a transport with the existing
JTAG-specific code.
In contrast to the current JTAG-only interface, the interface adds
support for two previously-missing (and unused) DAP operations:
- aborting the current AP transaction (untested);
- reading the IDCODE register (tested) ... required for SWD init.
The choice of transports may be fixed at the chip, board, or JTAG/SWD
adapter level. Or if all the relevant hardware supports both transport
options, the choice may be made at runtime, This patch provides basic
infrastructure to support whichever choice is made.
The current "JTAG-only" transport choice policy will necessarily continue
for now, until SWD support becomes available in OpenOCD. Later patches
start phasing out JTAG-specific calls in favor of transport-neutral calls.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add doxygen for target_resume() ... referencing the still-unresolved
confusion about what the "debug_execution" parameter means (not all
CPU support code acts the same).
The 'handle_breakpoints" param seems to have resolved the main issue
with its semantics, but it wasn't part of the function spec before.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Correct a mistake made copying the ID of the Cortex-M3 ETM module
from the TRM, so that "dap info" on a CM3 with an ETM will now
correctly describe ROM table entries for such modules. (They are
included on LPC17xx and some other cores.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The recent "add armv7m semihosting support" patch introduced two
build errors:
arm_semihosting.c: In function ‘do_semihosting’:
arm_semihosting.c:71: error: ‘spsr’ may be used uninitialized in this function
arm_semihosting.c:71: error: ‘lr’ may be used uninitialized in this function
This fixes those build errors. The behavior is, however, untested.
(Also, note the two new REVISIT comments.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
core_type check is not required as the core function will be
null for cores that do not support the mcr/mrc functions.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
do_semihosting and arm_semihosting now check the core type and
use the generic arm structure.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Move semihosting cmd to the arm cmd group.
Targets that support semihosting will setup the
setup_semihosting callback function.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
- Add arm cmd group to armv7m cmd chain.
- arm cmd's now check the core type before running a cmd.
- todo: add support for armv7m registers for reg cmd.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
- add mips support for target algorithms.
- added handlers for target_checksum_memory and target_blank_check_memory.
- clean up long lines
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
- armv7m_run_algorithm now requires all algorithms to use
a software breakpoint at their exit address
- updated all algorithms to support this
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Define two new DAP operations which use the new jtag_add_tms_seq()
calls to put the DAP's transport into either SWD or JTAG mode, when
the hardware allows.
Tested with the Stellaris 'Recovering a "Locked" Device' procedure,
which loops five times over both of these.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Highlight more of the internal JTAG-specific utilities, so it's
easier to identify code needing changes to become transport-neutral.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This allows minidrivers to e.g. hardware accelerate memory
writes.
Same trick as is used for arm7/9 dcc writes.
Added error propagation for memory transfer failures in
code rearrangement.
Also the JTAG end state is not updated until after
the memory write run is complete.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
When using an AP to access a memory (or a memory-mapped register),
some extra TCK (assuming JTAG) cycles should be added to ensure
the AP has enugh time to complete that access before trying to
collect the response.
The previous code was adding these cycles *before* trying to
access (read or write) data to that address, not *after*. Fix
by putting the delays in the right location.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This removes context-sensitivity from the programming interface and makes
it possible to know what a block of code does without needing to know the
previous history (specifically, the DAP's "trans_mode" setting).
The mode was only set to ATOMIC briefly after DAP initialization, making
this patch be primarily cleanup; almost everything depends on COMPOSITE.
The transactions which shouldn't have been queued were already properly
flushing the queue.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
I have no idea what the scan_inout_check() was *expecting* to achieve by
issuing a read of the DP_RDBUFF register. But in any case, that code was
clearly never being called ("invalue" always NULL) ... so remove it, and
the associated comment.
Also rename it as ap_write_check(), facilitating a cleanup of its single
call site by removing constant parameters.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
adi_jtag_dp_scan_u32() now wraps adi_jtag_dp_scan(), removing
code duplication. Include doxygen for the former. Comment
some particularly relevant points. Minor fault handling fixes
for both routines: don't register a callback that can't run,
or return ERROR_OK after an error.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Pass up fault codes from various routines, so their callers
can clean up after failures, and remove the FIXME comments
highlighting those previously goofy code paths.
dap_ap_{read,write}_reg_u32()
dap_ap_write_reg()
mem_ap_{read,write}_u32()
mem_ap_{read,write}_atomic_u32()
dap_setup_accessport()
Make dap_ap_write_reg_u32() just wrap dap_ap_write_reg(),
instead of cloning its core code (and broken fault handling).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Handling of AP (and AP register bank) selection, and cached AP
registers, is pretty loose ... start tightening it:
- It's "AP bank" select support ... there are no DP banks. Rename.
+ dap_dp_bankselect() becomes dap_ap_bankselect()
+ "dp_select_value" struct field becomes "ap_bank_value"
- Remove duplicate AP cache init paths ... only use dap_ap_select(),
and don't make Cortex (A8 or M3) cores roll their own code.
- For dap_ap_bankselect(), pass up any fault code from writing
the SELECT register. (Nothing yet checks those codes.)
- Add various bits of Doxygen
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Keep a handle to the PC in "struct arm", and use it.
This register is used a fair amount, so this is a net
minor code shrink (other than some line length fixes),
but mostly it's to make things more readable.
For XScale, fix a dodgy sequence while stepping. It
was initializing a variable to a non-NULL value, then
updating it to handle the step-over-active-breakpoint
case, and then later testing for non-NULL to see if
it should reverse that step-over-active logic. It
should have done like ARM7/ARM9 does: init to NULL.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Generalize the core of watchpoint setup so that it can handle
breakpoints too. Create breakpoint add/remove routines which
will use that, and hook them up to target types which don't
provide their own breakpoint support (nothing, yet).
This suffices for hardware-only breakpoint support. The ARM11
code will be able to switch over to this without much trouble,
since it doesn't yet handle software breakpoints. Switching
Cortex-A8 will be a bit more involved.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Address some FIXME comments by getting rid of globals, moving
per-core parameters in the existing per-core data structure.
This will matter most whenever there are multiple ARM11 cores,
e.g. ARM11 MPcore chips, but in general is just cleanup.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This sets up a few of the core "struct arm" data structures so they
can be used with ARMv7-M cores. Specifically, it:
- defines new ARM core_modes to match the microcontroller modes
(e.g. HANDLER not IRQ, and two types of thread mode);
- Establishes a new microcontroller "core_type", which can be
used to make sure v7-M (and v6-M) cores are handled right;
- adds "struct arm" to "struct armv7m" and arranges for the
target_to_armv7m() converter to use it;
- sets up the arm.core_cache and arm.cpsr values
- makes the Cortex-M3 code maintain arm.map and arm.core_mode.
This is currently set up as a parallel data structure, primarily to
minimize special cases for the semihosting support with microcontroller
profile cores.
Later patches can rip out the duplicative ARMv7-M support and start
reusing core ARM code.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The recent patch to fixbreakpoints and dcache handling added
a bunch of overlong lines (80+ chars) ... shrink them, and do
the same to a few lines which were already overlong.
Also add a few FIXME comments to nudge (a) replacement of some
magic numbers with opcode macros, which will be much better at
showing what's actually going on, and (b) correct return codes.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Breakpoints did not work because the data cache was not flushed
properly.
As a bonus add capability to write to memory marked as read only
by the MMU, which allows software breakpoints in such memory
regions.
For folk who don't know the ARM920 JTAG interface very well, the
two modes of scan chain 15 access to CP15 are confusing.
Make those parts of the ARM920 code less opaque, by:
- Adding comments referencing the relevant parts of the TRM,
catching up to similar updates in the User's Guide.
- Replacing magic numbers in physical access clients with
symbolic equivalents.
No functional change.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
When a DSP563xx-aware GDB asks OpenOCD for target registers,
the result should be a GDB with register data ... not an
OpenOCD crash.
(Note that mainline GDB doesn't currently support this core,
so for now, this requires a GDB with FreeScale patches.)
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This is a copy and paste of arm926ejs. Not tested, but
ready for testing at least. There is a good chance that
it will work if the generic armv4_5 fn's are robust enough...
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Copy of the 926ejs function. I have tested it only using
my rtems application (where virtual address mapping == physical).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
reset init would get stuck in an infinite loop when
e.g. khz was too high. Added timeout. This is a copy
of paste of a number of such bugfixes in the arm11
code.
Arm11 code reviewed for further such infinite loop bugs
and I couldn't find any more. Xing fingers it's the last
one...
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Provide doxygen for many of the public ADIv5 interfaces (i.e. the ones
called from Cortex core support code).
Add FIXMEs (and a TODO) to help resolve implementation issues which
became more apparent when trying to document this code:
- Error-prone context-sensitivity (queued/nonqueued) in many procedures.
- Procedures that lie by ignoring errors and wrongly claiming success.
Also, there was no point in a return from dap_ap_select(); it can't fail,
and no caller checks its return status. Clean that up, make it void.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Init the ARMv7-M magic number. Define predicate verifying it.
Use it to resolve a lurking bug/FIXME: make sure the ARMv7-M
specific DAP ops reject non-ARMv7-M targets.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The semihosting interface has a strange convention for read/write where
the unused amount of buffer must be returned. We failed to return the
total buffer size when the local read() call returned 0.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
srst_asserted and power_restore can now be overriden to do
nothing. By default they will "reset init" the targets and
halt gdb.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
When the TAR cache was explicitly invalidated, don't bother
printing it; the actual hardware status is more informative.
Provide some doxygen for the MEM-AP setup routine.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
If the MEM-AP cache is invalid, don't display it; just report that
invalidity as an error. (This bug has been observed with "mdw 0 32"
after just a "reset halt". Some code is being wrongly bypassed...)
If it's valid, display that cache at DEBUG level, not ERROR. Also,
don't assume it's an AHB-AP; it could be another flavor of MEM-AP.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Reject invalid AP numbers (256+) as Tcl operation parameters.
Shrink one of the overlong lines.
Add my copyright to the ADIv5 code (multiple contributions).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make messages reference "DAP" if they're actually transport-agnostic, or
"JTAG-DP" when they're JTAG-specific. Saying SWJ-DP is often wrong (on
most Cortex-A8 chips) and is confusing even if correct (since we don't
yet support SWD).
Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight
that it's JTAG-specific, and that identify DAP clients undesirably depending
on JTAG. (They will all need to change for SWD support.)
Shrink a few overlong lines of code. Copy a comment from code removed
in a previous patch (for the ARMv7-M "dap baseaddr" command).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Make the ARMv7-M DAP code reuse the command handler for "dap baseaddr".
For some reason, this DAP command wasn't converted earlier.
This is a code shrink and simplification; it also removes a needless
transport dependency on JTAG.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The term "DPM" is probably not well known ("Device Power Management"?),
so identify its source in the current ARM architecture specification.
It's relevant to ARMv6, ARMv7-A, and ARMv7-R ... but not "M" profiles.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Cygwin would fail to reopen a previously written file if the mode is
not given.
Simplified converting the open flags and made sure the win32 O_BINARY
bit is set.
Added define for systems that do not support O_BINARY.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
SYS_FLEN would be called before a write on a descriptor to check its size.
Currently lseek would fail with -1 when given the stdout/stderr descriptor.
Changing to use fstat seems to be the standard way of handling this.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
ARMv7-M defines a "lockup" state that's entered in certain double
fault sequences which can't be recovered from without external help.
OpenOCD has previously ignored this.
Issue a diagnostic saying the chip has locked up, and force exit
from this state by halting the core. It's not clear this is the
best way to handle lockup; but there should now be less confusion.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add space missing after the invalid ACK value. On init, say
which AP is being used, and don't assume it's an AHP-AP.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
If the target and openocd are idling, the log should normally
be silent at level 3. (Given no verbose logging options.)
Signed-off-by: Edgar Grimberg <edgar.grimberg@zylin.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
The breakpoint/watchpoint message was wrong for Feroceon and
Dragonite, which have only one working watchpoint unit.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This fixes a bug whereby GDB's breakpoints weren't activated.
The root cause is a confused interface to resume(). Fix by
almost ignoring the "handle breakpoints" parameter; it only
seems related to the case of skipping breakpoint-at-PC.
Update a few coments to clarify what's happening.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Doxygen: don't be needlessly verbose; alphabetically sort members
TODO: add random bits; clarify which manuals are referenced
ARM disassembler: mention a few opcodes that still aren't handled
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Update the comments about DP registers and some of the bitfields.
Remove inappropriate (and unused) DP_ZERO declaration.
Add some (currently unused) #defines needed for SWD protocol support,
based on previous patches from Andreas Fritiofson and Simon Qian.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
If GDB halts unexpectedly, print reason: srst assert or power
out detected.
If polling fails, then things are a bit trickier. We do not
want to spam telnet or the log with polling failed messages.
Leave that case be w/a comment in a code for now.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Skip over a bkpt instruction if found on resume/step.
Only software breakpoints known to OpenOCD are currently handled.
So this handles the special case of either a user added bkpt
or library added, eg. semi-hosting support.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
Don't just complain about an invalid ACK; say what the
value was, to help troubleshooting.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Until we manage breakpoints at runtime (patches not ready for 0.4)
the only way this code should touch them is to disable them at server
startup (a previous debug session may have left them active).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Add doxygen and other comments for what's more or less the lowest
level JDAG-DP primitive, to access JTAG_DP_{A,D}PACC registers.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Teach most remaining ARM cores how to use the "reset-assert" event.
Same model as elsewhere: iff a handler is provided for that event,
use that instead of trying to assert SRST (which may be unavailable,
or inappropriate since it resets too much). Else no change.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Shrink some overlong lines. Add my 2009 copyright.
Move a declaration to the beginning of its block.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This updates three aspects of debugger/exception interactions:
- Save the user's "vector_catch" setting, and restore it after reset.
Previously, it was obliterated (rather annoyingly) each time.
- Don't catch BusFault and HardFault exceptions unless the user says
to do so. Target firmware may need to handle them.
- Don't modify SHCSR to prevent escalating BusFault to HardFault.
Target firmware may expect to handle it as a HardFault.
Those simplifications fix several bugs. In one annoying case, OpenOCD
would cause the target to lock up on ome faults which triggered after
the debugger disconnected.
NOTE: a known remaining issue is that OpenOCD can still leave DEMCR
set after an otherwise-clean OpenOCD shutdown.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
DCC downloads should be enabled for any self repecting
openocd config file for arm7/9. Print out note about
it otherwise.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Allow targets to run checks post reset. Used to check
that e.g. DCC downloads have been enabled.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
Spencer Oliver
Øyvind Harboe
Marek Vasut
ddraskovic
Peter Stuge
Antonio Borneo
Mike Dunn
Oleksandr Tymoshenko
David Brownell
Edgar Grimberg
Jon Povey
Gary Carlson
Jun Ma
Anton Fedotov
Daniel Bäder
Bradey Honsinger
Marc Pignat
Mathias Kuester
Nicolas Pitre