ARM ADIv5: add comments
Add doxygen and other comments for what's more or less the lowest level JDAG-DP primitive, to access JTAG_DP_{A,D}PACC registers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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@ -88,7 +88,24 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
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* *
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***************************************************************************/
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/* Scan out and in from target ordered uint8_t buffers */
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/**
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* Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
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* conversions are performed. See section 4.4.3 of the ADIv5 spec, which
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* discusses operations which access these registers.
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*
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* Note that only one scan is performed. If RnW is set, a separate scan
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* will be needed to collect the data which was read; the "invalue" collects
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* the posted result of a preceding operation, not the current one.
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*
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* @param swjdp the DAP
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* @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
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* @param reg_addr two significant bits; A[3:2]; for APACC access, the
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* SELECT register has more addressing bits.
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* @param RnW false iff outvalue will be written to the DP or AP
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* @param outvalue points to a 32-bit (little-endian) integer
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* @param invalue NULL, or points to a 32-bit (little-endian) integer
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* @param ack points to where the three bit JTAG_ACK_* code will be stored
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*/
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static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
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uint8_t instr, uint8_t reg_addr, uint8_t RnW,
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uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
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@ -104,6 +121,7 @@ static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
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/* REVISIT these TCK cycles should be *AFTER* updating APACC, since
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* they provide more time for the (MEM) AP to complete the read ...
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* See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
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*/
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if ((instr == JTAG_DP_APACC)
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&& ((reg_addr == AP_REG_DRW)
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@ -111,12 +129,20 @@ static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
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&& (swjdp->memaccess_tck != 0))
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jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
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/* Scan out a read or write operation using some DP or AP register.
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* For APACC access with any sticky error flag set, this is discarded.
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*/
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fields[0].tap = jtag_info->tap;
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fields[0].num_bits = 3;
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buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
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fields[0].out_value = &out_addr_buf;
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fields[0].in_value = ack;
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/* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
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* complete; data we write is discarded, data we read is unpredictable.
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* When overrun detect is active, STICKYORUN is set.
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*/
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fields[1].tap = jtag_info->tap;
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fields[1].num_bits = 32;
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fields[1].out_value = outvalue;
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